VHDL parser should create relations for package without library
In order to be able to work with both VHDL and SystemVerilog, the VHDL
parser should not only create a package relation in the form of:
["Provide", "package", "<library_name>.<package_name>"],
["Provide", "package", "<package_name>"],
I only found the following way to use a VHDL package from SV:
this does not include the library where this package is defined.