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Opened Apr 13, 2016 by Andreas Bergmann (Consult)@bergya2
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Parameter is misinterprated and misinterpreted as (missing) module

The following RAM simulation module uses a predefined parameter, which is later used for defining a delay.

LINE 46: Tsa
used in Line 67 #Tsa

This construct seems to be misinterprated as a (missing hdl-module).
This is just a WARNING in scriptoutput and it seems to work fine. Anyway its a little bit uggly.

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  • IS61LV6416L.v
  • simple.v
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Reference: project/hdl-make#34