The FIFO size and full threshold need to be enough to hold if necessary all the pending read data
requests from the WB slave.

In the case of the Spartan-6 DDR controller being the WB slave, the FIFO needs to be able to store
up to 192 words (128 from the controller itself, plus 64 from our wrapper).

Since the GN4124 is used primarily on the SPEC, this is now the default value for the L2P DMA
master.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Remove the option to use the 200MHz PCI clock for the complete DMA engine to avoid compicating the design
and introducing too many alternatives that will need to be tested, now and in the future.

On the SPEC, it has been shown that with the latest modifications it is trivial to meet timing when using
a 125MHz (asynchronous to the PCI) clock for DMA.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Following up on 6c4dca2c, this commit fixes one issue related to resets and performs
further reset and clock-domain crossing (CDC) cleanup.

Important changes include:

1. Make sure that all dual async fifos are reset on both sides. This solves an issue
   with soft resets causing the host PC to hang.

2. Remove c_RST_ACTIVE constant to make the code simpler.

3. Remove reset from many signals (in particular from wide, data signals) that do not
   need to be reset. This helps with meeting timing wrt reset distribution.

4. Remove synchronizers from p2l deserializers, the SERDES outputs are already synced
   to the FPGA clock.

Important changes include:

1. Clear separation of resets per clock domain (with the exception
   of the wbgen-generated dma controller registers).

2. Conversion of all processes to use synchronous resets when the
   reset is synced with the clock of the process.

3. Use of standard synchronizers from general-cores when crossing
   clock-domains.

Due to the change in processes to use sync resets, a lot of code
has changed indentation. To this end, it might be useful to perform
a case insensitive diff when studying the changes of this commit.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Note: To avoid host hang in case of access to un-mapped address
      and user logic not asserting ERR signal.

core: Add err, rty and int signals to the wishbone masters interfaces. Terminate wb cycle in case of err on csr wb bus.

Note: The wb crossbar asserts err in case of access to un-mapped address.
      Therefore to avoid host hang in case of access to un-mapped address,
      the wb cycle is terminated (and returns 0xFFFFFFFF in case of read cycle).

tx_error acts as the abort signal.

Uses serdes and PLL for clocking.
IODELAY are bypassed on data inputs lines.
System clock in shifted 90deg compared to input p2l clock.