[hdl] test, verify and enable byte swap feature

hdl/rtl/dma_controller_regs.cheby

@@ -52,6 +52,11 @@ memory-map:
          name: byteswap
          range: 3-2
          description: Control byte-swapping
+         comment: |
+           - 00: ABCD -> ABCD
+           - 01: ABCD -> DCBA
+           - 10: ABCD -> CDAB
+           - 11: ABCD -> BADC
       x-hdl:
         write-strobe: True
         write-ack: True

hdl/rtl/spartan6/gn4124_core.vhd

@@ -586,7 +586,8 @@ begin
         g_ADDR_FIFO_FULL_SIZE  => g_L2P_ADDR_FIFO_FULL_SIZE,
         g_ADDR_FIFO_FULL_THRES => g_L2P_ADDR_FIFO_FULL_THRES,
         g_DATA_FIFO_FULL_SIZE  => g_L2P_DATA_FIFO_FULL_SIZE,
-        g_DATA_FIFO_FULL_THRES => g_L2P_DATA_FIFO_FULL_THRES)
+        g_DATA_FIFO_FULL_THRES => g_L2P_DATA_FIFO_FULL_THRES,
+        g_BYTE_SWAP            => TRUE)
       port map (
         clk_i   => sys_clk,
         rst_n_i => sys_rst_n,
@@ -632,7 +633,8 @@ begin
     cmp_p2l_dma_master : entity work.p2l_dma_master
       generic map (
         g_FIFO_SIZE         => g_P2L_FIFO_SIZE,
-        g_FIFO_FULL_THRES   => g_P2L_FIFO_FULL_THRES)
+        g_FIFO_FULL_THRES   => g_P2L_FIFO_FULL_THRES,
+        g_BYTE_SWAP         => TRUE)
       port map (
         clk_i   => sys_clk,
         rst_n_i => sys_rst_n,

hdl/rtl/spartan6/gn4124_core_pkg.vhd

@@ -230,9 +230,9 @@ package body gn4124_core_pkg is
   -- enable | byte_swap | din  | dout
   -- false  | XX        | ABCD | ABCD
   -- true   | 00        | ABCD | ABCD
-  -- true   | 01        | ABCD | BADC
+  -- true   | 01        | ABCD | DCBA
   -- true   | 10        | ABCD | CDAB
-  -- true   | 11        | ABCD | DCBA
+  -- true   | 11        | ABCD | BADC
   -----------------------------------------------------------------------------
   function f_byte_swap (
     constant enable    : boolean;
@@ -246,18 +246,18 @@ package body gn4124_core_pkg is
         when "00" =>
           dout := din;
         when "01" =>
-          dout := din(23 downto 16)
-                  & din(31 downto 24)
-                  & din(7 downto 0)
-                  & din(15 downto 8);
-        when "10" =>
-          dout := din(15 downto 0)
-                  & din(31 downto 16);
-        when "11" =>
           dout := din(7 downto 0)
                   & din(15 downto 8)
                   & din(23 downto 16)
                   & din(31 downto 24);
+        when "10" =>
+          dout := din(15 downto 0)
+                  & din(31 downto 16);
+        when "11" =>
+          dout := din(23 downto 16)
+                  & din(31 downto 24)
+                  & din(7 downto 0)
+                  & din(15 downto 8);
         when others =>
           dout := din;
       end case;

hdl/sim/example_tb/main.sv

@@ -114,7 +114,7 @@ module main;
 
    CBusAccessor acc;
 
-   task val_check(string name, uint64_t addr, val, expected);
+   task val_check(string name, uint32_t addr, val, expected);
       if (val != expected)
         begin
            $display();
@@ -124,7 +124,7 @@ module main;
         end
    endtask // val_check
 
-   task reg_check(uint64_t addr, expected);
+   task reg_check(uint32_t addr, expected);
       uint64_t val;
       acc.read(addr, val);
       val_check("Register read-back", addr, val, expected);
@@ -132,7 +132,10 @@ module main;
 
    initial begin
 
-      uint64_t addr, val, expected;
+      automatic int ntest = 1;
+      const     int tests = 6;
+
+      uint32_t addr, val, expected;
 
       @(posedge i_gn4124.ready);
 
@@ -142,7 +145,8 @@ module main;
 
       @(posedge clk_125m);
 
-      $write("Test 1/4: simple read/write accesses over Wishbone: ");
+      $write("Test %0d/%0d: simple read/write accesses over Wishbone: ",
+             ntest++, tests);
 
       // Verify simple read/writes over wishbone
       reg_check('h0, 'h0);
@@ -161,7 +165,8 @@ module main;
 
       $write("PASS\n");
 
-      $write("Test 2/4: 32 reads over DMA, abort after first read: ");
+      $write("Test %0d/%0d: 32 reads over DMA, abort after first read: ",
+             ntest++, tests);
 
       // Perform 32 reads over DMA
       reg_check('h00, 'h00000000);
@@ -176,7 +181,7 @@ module main;
       @(posedge i_gn4124.l2p_valid); // skip header
       @(posedge i_gn4124.l2p_valid);
 
-      expected = 64'h8000001f;
+      expected = 32'h8000001f;
       val = i_gn4124.l2p_data;
       @(posedge i_gn4124.l2p_clk_n);
       val |= i_gn4124.l2p_data << 16;
@@ -193,75 +198,52 @@ module main;
 
       $write("PASS\n");
 
-      $write("Test 3/4: 32 reads over DMA: ");
-
-      // Restart
-      acc.write('h14, 'h80); // count
-      acc.write('h00, 'h01); // start
-
-      @(posedge i_gn4124.l2p_valid); // skip header
-      @(posedge i_gn4124.l2p_valid);
-
-      for (addr = 'h20; addr > 'h00; addr -= 1)
-        begin
-           expected = 64'h80000000 + addr - 1;
-           val = i_gn4124.l2p_data;
-           @(posedge i_gn4124.l2p_clk_n);
-           val |= i_gn4124.l2p_data << 16;
-           val_check("DMA read-back", 'h20-addr, val, expected);
-           @(posedge i_gn4124.l2p_clk_p);
-        end
-
-      repeat(4) @(posedge clk_125m);
-
-      //  Check irq status
-      reg_check('h04, 'h04);
-      if (dma_irq != 1'b1)
-        $fatal(1, "dma irq should be 1");
-
-      // clear irq
-      acc.write('h04, 'h04);
-      reg_check('h04, 'h00);
-      if (dma_irq != 1'b0)
-        $fatal(1, "dma irq should be 0");
-
-      $write("PASS\n");
-
-      $write("Test 4/4: 16 reads over DMA: ");
-
-      // Restart
-      acc.write('h14, 'h40); // count
-      acc.write('h00, 'h01); // start
-
-      @(posedge i_gn4124.l2p_valid); // skip header
-      @(posedge i_gn4124.l2p_valid);
-
-      for (addr = 'h20; addr > 'h10; addr -= 1)
-        begin
-           expected = 64'h80000000 + addr - 1;
-           val = i_gn4124.l2p_data;
-           @(posedge i_gn4124.l2p_clk_n);
-           val |= i_gn4124.l2p_data << 16;
-           val_check("DMA read-back", 'h20-addr, val, expected);
-           @(posedge i_gn4124.l2p_clk_p);
-        end
-
-      repeat(4) @(posedge clk_125m);
-
-      //  Check irq status
-      reg_check('h04, 'h04);
-      if (dma_irq != 1'b1)
-        $fatal(1, "dma irq should be 1");
-
-      // clear irq
-      acc.write('h04, 'h04);
-      reg_check('h04, 'h00);
-      if (dma_irq != 1'b0)
-        $fatal(1, "dma irq should be 0");
-
-      $write("PASS\n");
-
-      #1us;
+      // Check all four byte swap settings
+      for (int i = 0; i < 4; i++) begin
+         $write("Test %0d/%0d: 32 reads over DMA (byte swap = %0d): ",
+                ntest++, tests, i);
+
+         // Restart
+         acc.write('h14, 'h80); // count
+         acc.write('h00, (i << 2) | 'h01); // start
+
+         @(posedge i_gn4124.l2p_valid); // skip header
+         @(posedge i_gn4124.l2p_valid);
+
+         for (addr = 'h20; addr > 'h00; addr -= 1)
+           begin
+              expected = 32'h80000000 + addr - 1;
+              if (i == 1)
+                expected = {<<8{expected}};
+              else if (i == 2)
+                expected = {<<16{expected}};
+              else if (i == 3)
+                expected = {<<16{{<<8{expected}}}};
+              val = i_gn4124.l2p_data;
+              @(posedge i_gn4124.l2p_clk_n);
+              val |= i_gn4124.l2p_data << 16;
+              val_check("DMA read-back", 'h20-addr, val, expected);
+              @(posedge i_gn4124.l2p_clk_p);
+           end
+
+         //#1us;
+         repeat(4) @(posedge clk_125m);
+
+         //  Check irq status
+         reg_check('h04, 'h04);
+         if (dma_irq != 1'b1)
+           $fatal(1, "dma irq should be 1");
+
+         // clear irq
+         acc.write('h04, 'h04);
+         reg_check('h04, 'h00);
+         if (dma_irq != 1'b0)
+           $fatal(1, "dma irq should be 0");
+
+         $write("PASS\n");
+
+         #1us;
+      end
 
       $display();
       $display("Simulation PASSED");