wb_uart: testbench with regression cases against different combinations of FIFOs & VUART functionality

wb_uart: temporary fix for eRTM UART FIFO issue causing RX data loss. VUART likely not working. FIX BEFORE MERGING!

Note: this is incompatible with the 'old' (pre-2023) firmwares of SIS83k/eRTM14, but had to be done at some point. Both cards
use the FPGen core, but with different memory maps. This patch attempts at unifying the map for both K7/KU FPGAs.

dsp: don't use generics (even statically evaluable) in case statement, it's not fully VHDL-compliant. Kudos to Tristan!

sim: bring back Wishbone BFM headers to the root sim/ directory to avoid include search patch issues

Affected modules (as far as I know): eRTM14/15 and sis83k.

Wraps an LM32, DPRAM, UART and indirect memory loader.

genrams: added g_implementation_hint RAM/FIFO attribute allowing to select the memory primitive used to implement the RAM.

Currently only works on Xilinx FPGAs (the choices being "ultra", "block", "distributed", and the default "auto") and is ignored in other platforms.

inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy

dsp/gc_pi_regulator.vhd : limit is a reserved word in AMS-VHDL (ghdl warning), changing to lim and removing unused signal.

dsp/gc_pi_regulator: synthesis fails when g_INTEGRATOR_BITS is bigger than 32 as the vhdl integer type is only 32 bits wide. Removing unused constants.