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Platform-independent core collection
Commit c808d5ad authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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dsp: don't use generics (even statically evaluable) in case statement, it's not… 

dsp: don't use generics (even statically evaluable) in case statement, it's not fully VHDL-compliant. Kudos to Tristan!
parent dc47828d
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Showing with 32 additions and 25 deletions
modules/dsp/gc_integer_divide.vhd
View file @ c808d5ad
...@@ -42,7 +42,7 @@ entity gc_integer_divide is ...@@ -42,7 +42,7 @@ entity gc_integer_divide is
b_i : in std_logic_vector(g_BITS-1 downto 0); b_i : in std_logic_vector(g_BITS-1 downto 0);
q_o : out std_logic_vector(g_BITS-1 downto 0); q_o : out std_logic_vector(g_BITS-1 downto 0);
start_i : in std_logic; start_i : in std_logic;
ready_o : out std_logic; ready_o : out std_logic;
done_o : out std_logic done_o : out std_logic
); );
...@@ -90,15 +90,17 @@ begin ...@@ -90,15 +90,17 @@ begin
when 2 => when 2 =>
alu_op1 <= (others => '0'); alu_op1 <= (others => '0');
alu_op2 <= d; alu_op2 <= d;
when g_BITS + 3 =>
alu_op1 <= (others => '0');
alu_op2 <= q;
when g_BITS + 4 =>
alu_op1 <= (others => '0');
alu_op2 <= r;
when others => when others =>
alu_op1 <= r_next; if state = g_BITS + 3 then
alu_op2 <= d; alu_op1 <= (others => '0');
alu_op2 <= q;
elsif state = g_BITS + 4 then
alu_op1 <= (others => '0');
alu_op2 <= r;
else
alu_op1 <= r_next;
alu_op2 <= d;
end if;
end case; end case;
end process; end process;
...@@ -140,7 +142,7 @@ begin ...@@ -140,7 +142,7 @@ begin
end process; end process;
done_o <= done; done_o <= done;
ready_o <= not busy; ready_o <= not busy;
-- busy_o <= busy; -- busy_o <= busy;
...@@ -151,15 +153,18 @@ begin ...@@ -151,15 +153,18 @@ begin
alu_sub <= n_sign; alu_sub <= n_sign;
when 2 => when 2 =>
alu_sub <= d_sign; alu_sub <= d_sign;
when g_BITS + 3 =>
alu_sub <= n_sign xor d_sign;
when g_BITS + 4 =>
alu_sub <= n_sign;
when others => when others =>
alu_sub <= '1'; if state = g_BITS + 3 then
alu_sub <= n_sign xor d_sign;
elsif state = g_BITS + 4 then
alu_sub <= n_sign;
else
alu_sub <= '1';
end if;
end case; end case;
end process; end process;
p_state_counter : process(clk_i) p_state_counter : process(clk_i)
begin begin
if rising_edge(clk_i) then if rising_edge(clk_i) then
...@@ -203,19 +208,21 @@ begin ...@@ -203,19 +208,21 @@ begin
d <= alu_result(g_BITS-1 downto 0); d <= alu_result(g_BITS-1 downto 0);
is_div_by_zero <= alu_eq and not (is_rem_i or is_signed_i); is_div_by_zero <= alu_eq and not (is_rem_i or is_signed_i);
when g_BITS + 3 => when others =>
q_o <= std_logic_vector(alu_result(g_BITS-1 downto 0));
when g_BITS + 4 => if state = g_BITS + 3 then
q_o <= std_logic_vector(alu_result(g_BITS-1 downto 0)); q_o <= std_logic_vector(alu_result(g_BITS-1 downto 0));
elsif state = g_BITS + 4 then
q_o <= std_logic_vector(alu_result(g_BITS-1 downto 0));
else
when others => -- 3..g_BITS+2 (g_BITS) divider iterations q <= q(g_BITS-2 downto 0) & alu_ge;
q <= q(g_BITS-2 downto 0) & alu_ge;
if alu_ge = '1' then if alu_ge = '1' then
r <= resize(alu_result, r'length); r <= resize(alu_result, r'length);
else else
r <= r_next; r <= r_next;
end if;
end if; end if;
end case; end case;
end if; end if;
......
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