This generic is dummy (does nothing), yet it is needed since the
generic component declaration in genram_pkg.vhd has such generic.
It has it, because the xilinx generic_dpram.vhd has such generic
and uses it.
TBD whether we want to attempt at providing similar functionality
for altera

The so-called "inferred_X_fifo" are basically generics fifos using
inferred rams blocks from altera or xilinx, depending the target
platform. That's why it makes more sense to move them to the "generic"
folder of genrams. This change forces to rename the "generic_X_fifo"
under "altera". Since these fifos are using the altera fifo  Megafunction,
are going to be called "altera_X_fifo". The Manifest has been changed accordingly.

The recent merge lost our Altera work-alike.

By using altsyncram directly, we get the follow benefits:
  * clear control of read-write resolution behaviour
  * can specify a mif file for initialization
  * eliminates warnings about dual-port clock inference timings

There were many constructs like this:
  gen_with_empty : if(g_with_empty) generate
    empty_o <= empty;
  end generate gen_with_empty;

If g_with_empty is true, then there are no warnings.
If g_with_empty is false, then empty_o is unset and empty is unused.

There is no improvement in performance/resource utilization to explicitly
cutting these signals. The optimizer will happily discard unused logic.

The alternative of adding
  gen_without_empty : if(not g_with_empty) generate
    empty_o <= 'X';
  end generate gen_without_empty;
will remove the empty_o unset warning, but not the empty unused warning.

This patch does make it possible for designs to  use empty_o without
setting g_with_empty; an error. On the other hand, those designs had
undefined behaviour before anyway, so they might have worked unreliably.

Unfortunately, Arria5 cannot do read-old-data for the same port.
This formulation describes a dual-ported RAM with:
  write-first/read-new-data for RW conflict on same port
  read-first /read-old-data for RW conflict between ports
... which is exactly what Arria5 supports (and Arria2 can do too).

Users of the generic_dpram should simply avoid simultaneous
RW on the same port, as the result is undefined (Altera != Xilinx).

Newer quartus versions recognized that the code describes write-first logic,
which requires combinatorial bypass logic. Unfortunately, this is also impossible
with two clocks. Thus they reject synthesis. This manifests as the WR endpoint
RX path failing to synthesize.

This is the equivalent of commit 53979d4f.

I have no idea why.

With 63, no dual port memory is inferred.
With 7, it all works peachy.

Why on earth it affects completely independent code I cannot explain.

genrams: increased width of internal byte select array to avoid compilation/synthesis errors on rams wider than 64 bits

Tomasz Wlostowski authored 13 years ago and Tomasz Wlostowski committed 12 years ago

Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.

Quartus will not process a 'file_open' call during synthesis,
so we can instead initialize the RAM with a vhdl constant.