This is necessary in order to properly "emulate" the previous implementation
of the gc_sync_ffs module.

Furthermore, a "new" module has been introduced, the gc_edge_detect, which
combines positive and negative pulse edge detection. gc_negedge and gc_posedge
have been rewritten to use internally the new gc_edge_detect.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Also perform cleanup of sync and edge modules.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Tomasz Wlostowski authored 5 years ago and Dimitris Lampridis committed 5 years ago

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Reported by Olof Olof Kindgren (@olofk). See also merge request !4

.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

This allows them to be used right after in component declarations.

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

Without this option, the two outputs of the module are in different clock domains. The frequency value is in the clk_in domain, while the "valid" flag is in the system clock domain.

With the new option, if set to TRUE, both outputs will be in the system clock domain.

This commit does three changes to gc_sync_word_wr:

1. It converts it to use internally gc_pulse_synchroniser2
2. It introduces a new "busy" output bit
3. It introduces a new generic, g_AUTO_WR which instructs the core to write a new word continously, without input from the user.

Maciej Lipinski authored 5 years ago and Dimitris Lampridis committed 5 years ago

This is needed for fixed-latency streamers. Module was written by Tom,
he added it to wr-cores whereas it belongs here, I've moved it.

added gc_dyn_extend_pulse.vhd where the width of the extended pulse comes as an input rather than a generic.

common/gc_i2c_slave: added option to allow automatic ACK of address byte without external user intervention

It seems that similar modules might be needed in other designs. The
added gc_async_signals_input_stage provides:
- synchronisation of input digital asynchronous pulses with the clock
- degliching (filter len config through generic)
- single-clock pulse generation
- extended pulses generation (config through generic)

The new gc_single_reset_gen can generate a single reset signal that
is synchronous with the system clock domain (input clk). The input
to the module is a vector of asynchronous reset signals, such as
PCIe reset or button. These input signals are synchronised with
the clock domain. Additionally, the powerup count-down is taken care
for by the module. The resulting single reset signal is passed through
a programmable number of flip-flops at the output (g_out_reg_depth)
so that the ISE optimizer has easier work with the global reset
funout.

This module is a generalized and (hopefully) improved version of the
spec_reset_gen.vhd that is copy+pasted into many SPEC-based designed.
It was suggested during a review of one of such designes that this
reset should be added to general-cores. This is the execution of this
feedback.

This module might be potentially integrated with the other available
reset-generation module (gc_reset.vhd).

gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;