common: adding gc_sync_register.

gc_sync_register is a multibit cross-clock domain synchronizer, with constrainable input delay, to
prevent sync delays with more than 1 clock cycle uncertainity. Used to synchronize counters
in dual-clock FIFOs.

For Xilinx devices, add this constraint to your UCF file

NET "*/gc_sync_register_in[*]" MAXDELAY=<faster_clock_period / 2 here>;

modules/common/Manifest.py

@@ -19,5 +19,6 @@ files = [	"gencores_pkg.vhd",
                 "gc_dyn_glitch_filt.vhd",
                 "gc_big_adder.vhd",
                 "gc_fsm_watchdog.vhd",
-                "gc_bicolor_led_ctrl.vhd"
+                "gc_bicolor_led_ctrl.vhd",
+                "gc_sync_register.vhd"
                 ];

modules/common/gc_sync_register.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+
+entity gc_sync_register is
+  generic (
+    g_width : integer);
+  port (
+    clk_i     : in  std_logic;
+    rst_n_a_i : in  std_logic;
+    d_i       : in  std_logic_vector(g_width-1 downto 0);
+    q_o       : out std_logic_vector(g_width-1 downto 0));
+
+end gc_sync_register;
+
+
+architecture rtl of gc_sync_register is
+
+  signal gc_sync_register_in : std_logic_vector(g_width-1 downto 0);
+  signal sync0, sync1        : std_logic_vector(g_width-1 downto 0);
+
+  attribute shreg_extract                        : string;
+  attribute shreg_extract of gc_sync_register_in : signal is "no";
+  attribute shreg_extract of sync0               : signal is "no";
+  attribute shreg_extract of sync1               : signal is "no";
+
+  attribute keep                        : string;
+  attribute keep of gc_sync_register_in : signal is "true";
+  attribute keep of sync0               : signal is "true";
+  attribute keep of sync1               : signal is "true";
+  
+begin
+
+  process(clk_i, rst_n_a_i)
+  begin
+    if(rst_n_a_i = '0') then
+      sync1 <= (others => '0');
+      sync0 <= (others => '0');
+    elsif rising_edge(clk_i) then
+      sync0 <= gc_sync_register_in;
+      sync1 <= sync0;
+    end if;
+  end process;
+
+  gc_sync_register_in <= d_i;
+  q_o                 <= sync1;
+  
+end rtl;

modules/common/gencores_pkg.vhd

@@ -8,7 +8,7 @@
 --              Matthieu Cattin
 -- Company    : CERN
 -- Created    : 2009-09-01
--- Last update: 2014-07-15
+-- Last update: 2014-07-31
 -- Platform   : FPGA-generic
 -- Standard   : VHDL '93
 -------------------------------------------------------------------------------
@@ -470,6 +470,16 @@ package gencores_pkg is
         );
   end component;
 
+  component gc_sync_register is
+    generic (
+      g_width : integer);
+    port (
+      clk_i     : in  std_logic;
+      rst_n_a_i : in  std_logic;
+      d_i       : in  std_logic_vector(g_width-1 downto 0);
+      q_o       : out std_logic_vector(g_width-1 downto 0));
+  end component gc_sync_register;
+
   --============================================================================
   -- Procedures and functions
   --============================================================================