The new gc_single_reset_gen can generate a single reset signal that
is synchronous with the system clock domain (input clk). The input
to the module is a vector of asynchronous reset signals, such as
PCIe reset or button. These input signals are synchronised with
the clock domain. Additionally, the powerup count-down is taken care
for by the module. The resulting single reset signal is passed through
a programmable number of flip-flops at the output (g_out_reg_depth)
so that the ISE optimizer has easier work with the global reset
funout.

This module is a generalized and (hopefully) improved version of the
spec_reset_gen.vhd that is copy+pasted into many SPEC-based designed.
It was suggested during a review of one of such designes that this
reset should be added to general-cores. This is the execution of this
feedback.

This module might be potentially integrated with the other available
reset-generation module (gc_reset.vhd).