Some signals are flat-out unused
 => these are outright removed
Some signals are used only under certain conditions
 => these have the definitions made also conditional

In Verilog, an "assign x = y;" will cause a warning in Quartus if x was not defined.
For example,
  Warning (10236): Verilog HDL Implicit Net warning at lm32_allprofiles.v(45398): created implicit net for "multiply"
This patch defines all such nets.

Also, the CSR width is too narrow by default (CFG2 must fit).

In case the free_clk itself is not running when the lock is lost,
still reset the other clock domains.

According to Peter Jansweijer, Precision and Questasim had trouble
synthesizing the crossbar HDL. After tracking the problem down via
email, it appears that these tools cannot handle nested functions
correctly; they crash or fail when trying to access the parameters
of the lexically enclosing function.

Therefore, this patch just outright removes all nested functions.

Unfortunately, Arria5 cannot do read-old-data for the same port.
This formulation describes a dual-ported RAM with:
  write-first/read-new-data for RW conflict on same port
  read-first /read-old-data for RW conflict between ports
... which is exactly what Arria5 supports (and Arria2 can do too).

Users of the generic_dpram should simply avoid simultaneous
RW on the same port, as the result is undefined (Altera != Xilinx).

The old version didn't do WE properly and was rather strangely coded.

Newer quartus versions recognized that the code describes write-first logic,
which requires combinatorial bypass logic. Unfortunately, this is also impossible
with two clocks. Thus they reject synthesis. This manifests as the WR endpoint
RX path failing to synthesize.

  * Only allocate FIFO space when a new operation is issued
  * Remove watchdog timeout which can violate WB signalling

  * Add an interrupt mask for legacy PCI.
  * Add bits to indicate whether a change to the control register is intended.
  * Made it possible to dequeue an operation without enqueueing an ack/err.

  * MSI and PCI interrupts in the altera mega-function
  * Restructure master/slave registers for bridge to be more
    readable regarding which address takes which action
  * Receive wishbone operations and use them to pulse interrupts
  * Added registers to indicate the address/data from WB

Each clock domain needs a separate reset line.
However, one cannot reset only a single domain---that could cause inconsistency
at clock crossing boundaries.
This change splits reset lines per clock domain and centralizes generation.

This is the equivalent of commit 53979d4f.

genrams/generic_shiftreg_fifo: don't clear the FIFO contents on reset (this was causing inference of FFs instead of SRLs)

Due to the way Altera uses padding, it is not possible to eliminate it without
the full state recovered during TLP decoding. Therefore, this version moves
the padding handling after the 64-32 conversion.

Furthermore, the decoding of TLP records now follows the PCIe 3.0 standard
instead of the slim Altera documentation. All incoming TLP formats should be
correctly processed without losing synchronization.