The subrange type might not be known in this context.
Fixes:
  wishbone_pkg.vhd:1379:26: object subtype is not locally static

Variable lengths might change; standard forbids length in a loop.
Fixes:
  wishbone_pkg.vhd:1576:18: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1613:18: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1734:30: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1771:16: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1806:16: universal integer bound must be numeric literal or attribute
  wishbone_pkg.vhd:1817:16: universal integer bound must be numeric literal or attribute

If a Wishbone master lowers the cycle line before receiving its acks, it is
non-conforming.  However, it is probably a good idea to not let an honest
slave (whose ack then comes in outside of the cycle) be penalized for that
master's misbehaviour.

This small change ensures the FIFO does not leak space in this case.

There was a bug in the wb_i2c_bridge that manifested itself a WB slave of the
wb_i2c_master module replies by an error to the write command. The bridge FSM
was buggy and was not clearing the WB signals, which led to the next WB transfer
in the sequence (any access to the I2C slave) failing.

This error was fixed by clearing the WB signals on error as well and the slave
now replies properly.

The WB signals are properly cleared on WB error in the case of a read, so this
issue does not exist.

Sometimes a master needs to stop the flow of acks.

If you use a PLL locked signal for reset, synchronous reset does
not work. That's b/c the clock doesn't run while reset is asserted.

One shouldn't do that, but sometimes it is convenient when testing.

Peter Jansweijer authored 11 years ago and Grzegorz Daniluk committed 10 years ago

Tried in real hardware and this works better.

Now wb_spi has generic parameters to configure registers length and number of
spi slaves. Reason for that is to keep default configuration in the repository
but also allow to adjust settings for WR Switch synthesis (and save resources).

The values used in WR Switch software fit in 8-bit registers so using 16-bits
in HDL was waste of resources.

Commit adds new WB register(IFS) that selects to which I2C interface master
should talk to. All other interfaces are then hold in idle state. IFS contains
also BUSY bit that is written only by host and marks that I2C Master is
currently in use and cannot be switched to another I2C interface. Host must
clear BUSY flag after the interaction with I2C interface is finished.

Even when g_num_pins was a small number, the registers inside were 32-bits, e.g. for g_num_pins=1 the module utilized 65 slice registers.

This is done to better reflect the interface of the module (structured Wishbone).
The documentation of the module is also changed in this respect.

If a very fast WB master queues a single-byte SPI command followed
immediately by the execute instruction, the SPI command will use
the old data in the FIFO. This delays execution by 1 cycle.

It was causing the simulation to fail with designs containing a xwb_register_link component.

the sdb address of the wb crossbar. The sdb address
is store in a CSR, 0xb, and it can be retrieved from the
firmware using an asm macro call.

Using the volatile configuration register to configure a flash chip
is a bad idea. The problem is that if the FPGA is reset, the flash
may be in a state inconsistent with what the FPGA requires to boot.

The correct solution is to configure the non-volatile configuration
register on the chip to what the FPGA expects on power-on. Then use
these same settings inside the flash core.

Going this route makes it necessary for software to be able to set
the non-volatile configuration register. Rather than making the core
even more complicated than it is, I have elected to add a FIFO which
software can fill to issue custom SPI commands. Since erase can only
be done from software anyway, I removed this code and let erase use
the custom command FIFO.

Comparing std_logic <= '0' seems to work!
However, it is certainly not what the author intended.

This is done by adding a generic to the entity, which is connected directly to
the gc_fsm_watchdog component instantiated within the wb_i2c_bridge. The user
should calculate the appropriate watchdog timeout value and set it via this
generic.

The instantiation template in the wishbone_pkg is also updated.

Signed-off-by: Theodor Stana <t.stana@cern.ch>

Theodor-Adrian Stana authored 11 years ago and Tomasz Wlostowski committed 11 years ago

Bridge: Removed "redundant" SIM_WB_TRANSFER state.

Slave: Removed redundant ADDR_CHECK state and moved its code to
the ADDR state.

Also corrected a bug whereby the ack_i pin was not being checked within
the ADDR_ACK state. This was causing the FSM to advance even thogh the
slave was actually NACK-ing.

DOC: Updated documentation for both these modules

Signed-off-by: Theodor Stana <t.stana@cern.ch>