wb_i2c_bridge: Fixed write to unknown address bug

There was a bug in the wb_i2c_bridge that manifested itself a WB slave of the
wb_i2c_master module replies by an error to the write command. The bridge FSM
was buggy and was not clearing the WB signals, which led to the next WB transfer
in the sequence (any access to the I2C slave) failing.

This error was fixed by clearing the WB signals on error as well and the slave
now replies properly.

The WB signals are properly cleared on WB error in the case of a read, so this
issue does not exist.

modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd

@@ -343,6 +343,9 @@ begin
               state  <= SYSMON_WR;
             elsif (wb_err = '1') then
               err_p_o <= '1';
+              wb_cyc  <= '0';
+              wb_stb  <= '0';
+              wb_we   <= '0';
               state   <= IDLE;
             end if;