xwb_clock_crossing: be more forgiving to pushy masters

If a Wishbone master lowers the cycle line before receiving its acks, it is
non-conforming.  However, it is probably a good idea to not let an honest
slave (whose ack then comes in outside of the cycle) be penalized for that
master's misbehaviour.

This small change ensures the FIFO does not leak space in this case.

modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd

@@ -188,7 +188,7 @@ begin
    end process;
 
    -- Master clock domain: master -> sFIFO
-   sw_en <= mrecv.CYC and (master_i.ACK or master_i.ERR or master_i.RTY);
+   sw_en <= master_i.ACK or master_i.ERR or master_i.RTY;
    ssend.ACK <= master_i.ACK;
    ssend.ERR <= master_i.ERR;
    ssend.RTY <= master_i.RTY;