- Nov 10, 2018
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They finally don't help much and they break simulation as Modelsim complains about types conversion.
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- Aug 16, 2017
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Grzegorz Daniluk authored
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- Aug 08, 2017
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Grzegorz Daniluk authored
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- Dec 09, 2014
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The simulator is crashing at the end of the LM32 startup code when it tries to access the highest RAM location (at the stack pointer). After this access, the LM32 verilog code already increments the address to be prepared for the next cycle, which will never actually happen because you are at the end of the RAM. It is this address increment in verilog that is one address outside the defined RAM array for which the simulator complains and terminates. The actual synthesized code is perfectly fine; no accesses outside RAM.
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- Mar 05, 2013
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Wesley W. Terpstra authored
The RW ordering on address conflict varies by platform. Some platforms only support some options. Most of the dprams in WR are portable and don't depend on the order. This new option allows a core to specify that it does not care what the result of a RW conflict is, and thus work on more platforms. For Xilinx, "dont_care" = "read_first", the old default.
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Wesley W. Terpstra authored
In the past we used a generic to set the initial memory contents on altera. Unfortunately, quartus compiles big generics slowly (read: hours). Now we can load from a .mif file instead, which is much faster (seconds). Thus, this old option is no longer needed.
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- Mar 28, 2012
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
genrams/xilinx/generic_dpram: made two separate versions for memories with both ports clocked with the same signal and with independent clocks This is to prevent ISE from interpreting the single-clock template as a dual-clock one, which may result in read-after-write memory content corruption on Spartan-6/Virtex-6 FPGAs.
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Genrams is a collection of synthesizable RAM/FIFO providing identical interface and features on different FPGA platforms.
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- Mar 13, 2012
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Wesley W. Terpstra authored
Quartus will not process a 'file_open' call during synthesis, so we can instead initialize the RAM with a vhdl constant.
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- Jan 24, 2012
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Tomasz Wlostowski authored
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- Nov 02, 2011
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Tomasz Wlostowski authored
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- Nov 01, 2011
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Tomasz Wlostowski authored
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- Oct 25, 2011
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Tomasz Wlostowski authored
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- Oct 04, 2011
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Tomasz Wlostowski authored
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- May 11, 2011
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
This reverts commit ae005148.
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Tomasz Wlostowski authored
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- May 02, 2011
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Tomasz Wlostowski authored
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