modules/genrams/xilinx/generic_dpram_dualclock.vhd · 487570132532eafeb750945a2f0d81f38e33dd00 · Projects / Platform-independent core collection · GitLab

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genrams/xilinx: remove optimizations for ram initialization · 48757013
Grzegorz Daniluk authored 7 years ago and Tomasz Wlostowski committed 6 years ago
```
They finally don't help much and they break simulation as Modelsim complains
about types conversion.
```
48757013