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Created with Raphaël 2.2.019Aug146324Jul1716973123Jun25May1913116430Apr24232120191614119732130Mar26171311654325Feb2019171330Jan2923222117161513Dec1111Nov425Oct242322211814827Sep191110929Aug762129Jul24191615111019Jun171454331May282320161087629Apr262524171211226Mar1411765413Feb130Jan2824221014Dec1130Nov2920161087331Oct2919121117Sep13111010Aug763230Jul2719Jun829May2329Apr26Mar2523201916141398529Feb30Jan2314Dec1328Nov171331Oct111027Sep625Aug221816151084323Jun2May16Mar28Feb2720171410326Jan15Dec29Nov28231727Oct1713527Sep30Aug252416Jun26Apr22216130Mar6Jan18Nov1716121Oct12Aug7Jul315Apr25Feb24179Dec14Aug431Jul1730Jun10522May21201530Apr2517144128Mar20527Feb2614621Jan14920Dec1816429Nov2826221530Oct25241824Sep1893230Aug2822147529Jul24Jun22May211086330Apr262523Fixed UARTs too short delay between RX read and ACKFixed bad wb_slave_adapter generics in crossbar sdb romsxwb_axi4lite_bridge: correctly resolve burststom-10g-hackstom-10g-hacksgc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed togethertom-afcz-aug25tom-afcz-aug25inferred_sync_fifo.vhd: Avoided error 10416: predefined attribute instance_name is not supported Filexwb_xc7_fw_update: Avoided error 10481: design library unisim does not contain primary unit vcomponentsmerged with masterMerge tag 'v1.1.0' into proposed_masterMerge branch 'release/1.1.0'v1.1.0v1.1.0bld: update CHANGELOGinferred_sync_fifo: fix full flag for g_show_ahead.Merge branch 'proposed_master' into release/1.1.0wb_fine_pulse_gen: simplify clock crossingstom-jun30 tom-s…tom-jun30 tom-sis83k-aug25sim: create accessor object to WB master interface as singletonfixed reading issue occuring when stall and ack are changing at the same timepeter_proposed_…peter_proposed_spec7_v5Initial committrivial fixML-new_wrs-4_re…ML-new_wrs-4_resource_eval[hdl] add missing default values to generic_sync_fifo thresholdsfixed reading issue occuring when stall and ack are changing at the same timespec7_v4.2 prop…spec7_v4.2 proposed_spec7sim/if_wb_master: return accessor object as a singletontom-proposed-ma…tom-proposed-master-jun30xwb_fine_pulse_gen: support for fine delay (ODELAYE3) on Kintex Ultrascalegc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed togetherxwb_simple_uart: fixed typo causing a parse error...wb_simple_uart: allow preset baudrate register through a genericgc_enc_8b10b: added missing signals on process sensitivity listwb_fine_pulse_gen: use double clock rate on Kintex7 Ultrascale, allowing for 1ns resolutionwb_fine_pulse_gen: implement separate serdes/PLL reset and lock indicator (required to maintain correct phase of the output pulses)wb_fine_pulse_gen: extend WB registers with separate serdes reset and PLL lock indicatorxwb_fine_pulse_gen: fix PLL instantiation on Kintex Ultrascalewishbone: added Fine Pulse Generator moduleaxi4: add 512-bit data width AXI4-full record, fixed compilation issue in axi->wb bridgexwb_lm32: don't include wr_node/mockturtle profile in the VHDL wrappersim/if_wb_master: return accessor object as a singletonxwb_fine_pulse_gen: support for fine delay (ODELAYE3) on Kintex UltrascaleInitial commitsim: create accessor object to WB master interface as singletonAdd wb_xc7_fw_update module.gc_simple_spi_master: keep MOSI at 0 when inactive so that multi-master SPI signals can be just ORed togethertom-may13tom-may13Merge remote-tracking branch 'origin/tom-ertm14' into tom-fine-pulse-gen-apr01common: added a simple non-WB SPI master