* Add an interrupt mask for legacy PCI.
  * Add bits to indicate whether a change to the control register is intended.
  * Made it possible to dequeue an operation without enqueueing an ack/err.

  * MSI and PCI interrupts in the altera mega-function
  * Restructure master/slave registers for bridge to be more
    readable regarding which address takes which action
  * Receive wishbone operations and use them to pulse interrupts
  * Added registers to indicate the address/data from WB

Each clock domain needs a separate reset line.
However, one cannot reset only a single domain---that could cause inconsistency
at clock crossing boundaries.
This change splits reset lines per clock domain and centralizes generation.

This is the equivalent of commit 53979d4f.

genrams/generic_shiftreg_fifo: don't clear the FIFO contents on reset (this was causing inference of FFs instead of SRLs)

Due to the way Altera uses padding, it is not possible to eliminate it without
the full state recovered during TLP decoding. Therefore, this version moves
the padding handling after the 64-32 conversion.

Furthermore, the decoding of TLP records now follows the PCIe 3.0 standard
instead of the slim Altera documentation. All incoming TLP formats should be
correctly processed without losing synchronization.

Remove SDC constraints which apply to megafunction options we do not use.

to ensure stabilization.

There is only one set of registers per read TLP data.

This used to be safe before the previous commit added STB outside of CYC.

Must detect BAR change during address decode.

Some Atom processors can not map so large a BAR.

Stall bar transitions when ACKs are inflight