Fixed address decoding (width was wrong)

Stall bar transitions when ACKs are inflight

modules/wishbone/wb_pcie/pcie_tlp.vhd

@@ -136,7 +136,6 @@ begin
           when h_low_addr =>
             -- address also stores busnum/devnum/ext/reg for IO ops
             r_address(31 downto 2) <= rx_wb_dat_i(31 downto 2);
-            r_bar <= rx_wb_bar_i;
           when p_w0 => null;
           when p_wx => null;
           when p_we => null;
@@ -182,7 +181,8 @@ begin
               next_state := h_low_addr;
             end if;
           when h_low_addr =>
-            if rx_wb_stb_i = '1' then
+            if (rx_wb_stb_i and not wb_stall_i) = '1' then
+              r_bar <= rx_wb_bar_i;
               if r_fmttype(6) = '1' then
                 next_state := p_w0;
               else
@@ -259,7 +259,11 @@ begin
           when h_completion2 => null;
           when h_request => null;
           when h_high_addr => null;
-          when h_low_addr => null;
+          when h_low_addr =>
+            -- If ACKs are inflight and the bar needs to change, stall
+            if r_bar /= rx_wb_bar_i and r_flight_count /= 0 then
+              r_always_stall <= '1';
+            end if;
           when p_w0 =>
             r_never_stall <= '0';
             r_never_stb <= '0';

modules/wishbone/wb_pcie/pcie_wb.vhd

@@ -49,7 +49,7 @@ architecture rtl of pcie_wb is
   
   -- control registers
   signal r_cyc   : std_logic;
-  signal r_addr  : std_logic_vector(31 downto 24);
+  signal r_addr  : std_logic_vector(31 downto 16);
   signal r_error : std_logic_vector(63 downto  0);
 begin
 
@@ -125,8 +125,8 @@ begin
                  r_error(31 downto  0);
   
   slave_i.cyc <= r_cyc;
-  slave_i.adr(31 downto 24) <= r_addr(31 downto 24);
-  slave_i.adr(23 downto 0)  <= wb_adr(23 downto 0);
+  slave_i.adr(r_addr'range) <= r_addr;
+  slave_i.adr(r_addr'right-1 downto 0)  <= wb_adr(r_addr'right-1 downto 0);
   
   control : process(internal_wb_clk)
   begin
@@ -136,20 +136,26 @@ begin
         r_error <= r_error(r_error'length-2 downto 0) & slave_o.err;
       end if;
       
-      -- Feedback acks one cycle after strobe
-      r_ack <= wb_stb;
-      r_high <= wb_adr(2);
-      
-      -- Is this a write to the register space?
-      if wb_bar = "000" and slave_i.we = '1' then
-        if wb_stb = '1' then
+      -- Is the control BAR targetted?
+      if wb_bar = "000" then
+        -- Feedback acks one cycle after strobe
+        r_ack <= wb_stb;
+        r_high <= wb_adr(2);
+		  
+		  -- Is this a write to the register space?
+        if wb_stb = '1' and slave_i.we = '1' then
           -- Cycle line is high bit of register 0
-          if wb_adr(7 downto 2) = "00000" and slave_i.sel(3) = '1' then
+          if wb_adr(6 downto 2) = "00000" and slave_i.sel(3) = '1' then
             r_cyc <= slave_i.dat(31);
           end if;
           -- Address 20 is low word of address window (register 2)
-          if wb_adr(7 downto 2) = "00101" and slave_i.sel(3) = '1' then
-            r_addr(31 downto 24) <= slave_i.dat(31 downto 24);
+          if wb_adr(6 downto 2) = "00101" then
+            if slave_i.sel(3) = '1' then
+              r_addr(31 downto 24) <= slave_i.dat(31 downto 24);
+            end if;
+            if slave_i.sel(2) = '1' then
+              r_addr(24 downto 16) <= slave_i.dat(24 downto 16);
+            end if;
           end if;
         end if;
       end if;