Conflicts:

	modules/common/Manifest.py
	modules/common/gencores_pkg.vhd

The LM32 needs a read-enable.
Unfortunately, Xilinx does not have one, so we emulate it.

By using altsyncram directly, we get the follow benefits:
  * clear control of read-write resolution behaviour
  * can specify a mif file for initialization
  * eliminates warnings about dual-port clock inference timings

On Altera, "" generates a null-range warning.
When the dpram is used heavily, these warnings add up to many.

The RW ordering on address conflict varies by platform.
Some platforms only support some options.
Most of the dprams in WR are portable and don't depend on the order.
This new option allows a core to specify that it does not care what
the result of a RW conflict is, and thus work on more platforms.

For Xilinx, "dont_care" = "read_first", the old default.

On both Altera and Xilinx, a dual port memory can achieve twice the
bit-width per memory block when there is a single reader and writer.
This adds a place-holder generic_simple_dpram for Xilinx so that code
using the purpose-built variant for Altera continues to work on ISE.

In the past we used a generic to set the initial memory contents on altera.
Unfortunately, quartus compiles big generics slowly (read: hours).
Now we can load from a .mif file instead, which is much faster (seconds).
Thus, this old option is no longer needed.

There were many constructs like this:
  gen_with_empty : if(g_with_empty) generate
    empty_o <= empty;
  end generate gen_with_empty;

If g_with_empty is true, then there are no warnings.
If g_with_empty is false, then empty_o is unset and empty is unused.

There is no improvement in performance/resource utilization to explicitly
cutting these signals. The optimizer will happily discard unused logic.

The alternative of adding
  gen_without_empty : if(not g_with_empty) generate
    empty_o <= 'X';
  end generate gen_without_empty;
will remove the empty_o unset warning, but not the empty unused warning.

This patch does make it possible for designs to  use empty_o without
setting g_with_empty; an error. On the other hand, those designs had
undefined behaviour before anyway, so they might have worked unreliably.

CFG_EBA_RESET is supposed to be the default value of the LM32's eba_reset
parameter. Unfortunately, the constant leaked into the sources directly.

In order to clean-up a truncation warning for pc_f, it was easiest to fix
the missing parameter and then use a subarray of that value.

Some signals are flat-out unused
 => these are outright removed
Some signals are used only under certain conditions
 => these have the definitions made also conditional

In Verilog, an "assign x = y;" will cause a warning in Quartus if x was not defined.
For example,
  Warning (10236): Verilog HDL Implicit Net warning at lm32_allprofiles.v(45398): created implicit net for "multiply"
This patch defines all such nets.

Also, the CSR width is too narrow by default (CFG2 must fit).

In case the free_clk itself is not running when the lock is lost,
still reset the other clock domains.

According to Peter Jansweijer, Precision and Questasim had trouble
synthesizing the crossbar HDL. After tracking the problem down via
email, it appears that these tools cannot handle nested functions
correctly; they crash or fail when trying to access the parameters
of the lexically enclosing function.

Therefore, this patch just outright removes all nested functions.

Unfortunately, Arria5 cannot do read-old-data for the same port.
This formulation describes a dual-ported RAM with:
  write-first/read-new-data for RW conflict on same port
  read-first /read-old-data for RW conflict between ports
... which is exactly what Arria5 supports (and Arria2 can do too).

Users of the generic_dpram should simply avoid simultaneous
RW on the same port, as the result is undefined (Altera != Xilinx).

The old version didn't do WE properly and was rather strangely coded.

Newer quartus versions recognized that the code describes write-first logic,
which requires combinatorial bypass logic. Unfortunately, this is also impossible
with two clocks. Thus they reject synthesis. This manifests as the WR endpoint
RX path failing to synthesize.

  * Only allocate FIFO space when a new operation is issued
  * Remove watchdog timeout which can violate WB signalling

  * Add an interrupt mask for legacy PCI.
  * Add bits to indicate whether a change to the control register is intended.
  * Made it possible to dequeue an operation without enqueueing an ack/err.

  * MSI and PCI interrupts in the altera mega-function
  * Restructure master/slave registers for bridge to be more
    readable regarding which address takes which action
  * Receive wishbone operations and use them to pulse interrupts
  * Added registers to indicate the address/data from WB