- 12 Jul, 2022 6 commits
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Adam Wujek authored
fmc-fdelay-pulse does not set pulse width to 50% by default due to the bug in it. Signed-off-by:Adam Wujek <dev_public@wujek.eu>
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Adam Wujek authored
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Adam Wujek authored
But still some improvements could be done... Signed-off-by: -
Adam Wujek authored
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Adam Wujek authored
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Adam Wujek authored
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- 21 Mar, 2022 2 commits
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Adam Wujek authored
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Adam Wujek authored
And compile fmc-tdc-list by default. Signed-off-by:
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- 19 Mar, 2022 15 commits
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Adam Wujek authored
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Adam Wujek authored
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Adam Wujek authored
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Adam Wujek authored
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Adam Wujek authored
After app metadata changed to 0x4000 according to the svec_base requirements Signed-off-by: -
Adam Wujek authored
Rollback in the commit 745e912c rollback to version before dlamprid commit (split channel CSR from FIFO readout) was not complete. This commit rollbacks the wb files. Signed-off-by:
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Adam Wujek authored
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Adam Wujek authored
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Adam Wujek authored
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Adam Wujek authored
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Federico Vaga authored
Signed-off-by:Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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Federico Vaga authored
Mainly software Signed-off-by: -
Federico Vaga authored
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Federico Vaga authored
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- 01 Mar, 2022 1 commit
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Evangelia Gousiou authored
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- 25 Feb, 2022 1 commit
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Evangelia Gousiou authored
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- 29 Jul, 2021 2 commits
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Federico Vaga authored
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Federico Vaga authored
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- 11 Dec, 2020 1 commit
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Federico Vaga authored
At the end the carrier offset value for White-Rabbit has been always constant and it depends on the hardware: - SVEC: 3000 ps - SPEC: 0 ps so, instead of complicate users life by setting this module parameter, here I am embedding it into the platform_data for the TDC. The ideal solution would be to ignore this value in software and to apply it in HDL directly. Signed-off-by:
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- 09 Dec, 2020 1 commit
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Federico Vaga authored
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- 04 Dec, 2020 2 commits
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Federico Vaga authored
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Federico Vaga authored
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- 18 Nov, 2020 2 commits
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Federico Vaga authored
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Federico Vaga authored
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- 17 Nov, 2020 6 commits
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Federico Vaga authored
8.0.0.rc1 - 2020-11-17 ====================== Added ----- - hdl,sw: double buffering DMA support for faster timestamping - hdl,sw: design built on top of spec-base and svec-base - tst: integration tests with pytest
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Federico Vaga authored
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Federico Vaga authored
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Tristan Gingold authored
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Tristan Gingold authored
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Federico Vaga authored
wbgen2 does not generate the correct header file, wrong offset. Signed-off-by:
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- 16 Nov, 2020 1 commit
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Federico Vaga authored
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