Commit f620300d authored by Federico Vaga's avatar Federico Vaga

Merge branch 'release/v8.0.0.rc1' into master

parents b10c63a4 d81325e5
......@@ -12,4 +12,15 @@ transcript
work/
NullFile
*.orig
*.html
\ No newline at end of file
*.html
*.o
*.ko
*~
*.mod.c
/.tmp_versions
.*cmd
modules.order
Module.symvers
*TAGS
GPATH
Makefile.specific
[submodule "ip-cores/general-cores"]
[submodule "hdl/ip-cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
[submodule "zio"]
path = software/zio
url = git://ohwr.org/misc/zio.git
..
SPDX-License-Identifier: CC-0.0
SPDX-FileCopyrightText: 2019 CERN
=========
Changelog
=========
8.0.0.rc1 - 2020-11-17
======================
Added
-----
- hdl,sw: double buffering DMA support for faster timestamping
- hdl,sw: design built on top of spec-base and svec-base
- tst: integration tests with pytest
Changed
-------
- drv,lib: API change fmctdc_buffer_mode() -> fmctdc_transfer_mode()
This diff is collapsed.
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modules = {"local": [
"hdl/rtl",
"hdl/top/spec"] };
modules = {
"local" : [
"hdl/rtl",
],
}
Subproject commit b84d0335dcda7b55352a3aabd38f65cf2169cac2
etherbone-core @ 84894459
Subproject commit 8489445985ff2afe6c72712014a92a271869f20a
Subproject commit 5205d9754b1e0887df5914a47f8aa745e4f3c2fe
Subproject commit 347e0de1e0d91834d298a146569530b71adeb33a
Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
Subproject commit 461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
Subproject commit c3ffa27d348645cad57d09af56cf0001be9e5077
Subproject commit 1b803764d842462233fb479d4cc0aa5418a9109f
Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
Subproject commit 69cc4cc3132530c836cd57ce1b282e8377fe7a07
Subproject commit a72a4223e2e1b521ba839f5623ee2857cf4fae10
files = [
"tdc_core_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd"
"tdc_core_pkg.vhd",
"reg_ctrl_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"channel_regs.vhd",
"channel_regs_wbgen2_pkg.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd",
"timestamp_convert_filter.vhd",
"tdc_dma_channel.vhd",
"tdc_dma_engine.vhd",
"tdc_buffer_control_regs.vhd",
"tdc_buffer_control_regs_wbgen2_pkg.vhd",
"tdc_ts_addsub.vhd",
"tdc_ts_sub.vhd",
"wbgen2_eic_nomask.vhd",
"dma_eic.vhd",
"tdc_onewire_wb.vhd",
"tdc_onewire_wbgen2_pkg.vhd"
];
This diff is collapsed.
......@@ -12,24 +12,10 @@
---------------------------------------------------------------------------------------------------
-- File acam_timecontrol_interface.vhd |
-- |
-- Description interface with the ACAM chip pins for control and timing. |
-- Description Interface with the ACAM chip pins for control and timing. |
-- the start pulse is sent only once upon the activation of the acquisition, |
-- synchronously to the utc_p_i |
-- |
-- |
-- Authors Gonzalo Penacoba (Gonzalo.Penacoba@cern.ch) |
-- Evangelia Gousiou (Evangelia.Gousiou@cern.ch) |
-- Date 04/2012 |
-- Version v0.11 |
-- Depends on |
-- |
---------------- |
-- Last changes |
-- 05/2011 v0.1 GP First version |
-- 04/2012 v0.11 EG Revamping; Comments added, signals renamed |
-- 04/2014 v2 EG Changed the generation of the start_from_fpga; synchronous to utc_p and |
-- after the signalling from the data_engine that state_active_p_i |
-- |
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
......@@ -52,11 +38,11 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.gencores_pkg.all;
......@@ -66,51 +52,37 @@ use work.gencores_pkg.all;
entity acam_timecontrol_interface is
port
-- INPUTS
-- INPUTS
-- Signals from the clk_rst_manager unit
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- reset
acam_refclk_r_edge_p_i : in std_logic; -- pulse upon ACAM RefClk rising edge
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- reset
-- upc_p from the WRabbit or the local generator
utc_p_i : in std_logic;
-- upc_p from the WRabbit or the local generator
utc_p_i : in std_logic;
-- Signals from the data_engine unit
state_active_p_i : in std_logic; -- the core ready to follow the ACAM EF
-- Signals from the data_engine unit
state_active_p_i : in std_logic; -- the core ready to follow the ACAM EF
-- Signals from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- signal from GN4124/VME to start following the ACAM chip
-- for tstamps aquisition
deactivate_acq_p_i : in std_logic; -- acquisition deactivated
-- Signals from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- signal from GN4124/VME to start following the ACAM chip
-- for tstamps aquisition
deactivate_acq_p_i : in std_logic; -- acquisition deactivated
-- Signals from the ACAM chip
err_flag_i : in std_logic; -- ACAM error flag, active HIGH; through ACAM config
-- reg 11 is set to report for any HitFIFOs full flags
int_flag_i : in std_logic; -- ACAM interrupt flag, active HIGH; through ACAM config
-- reg 12 it is set to the MSB of Start#
-- OUTPUTS
-- Signals to the ACAM chip
start_from_fpga_o : out std_logic;
-- OUTPUTS
-- Signals to the ACAM chip
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic;
-- Signals to the
acam_errflag_r_edge_p_o : out std_logic; -- ACAM ErrFlag rising edge
acam_errflag_f_edge_p_o : out std_logic; -- ACAM ErrFlag falling edge
acam_intflag_f_edge_p_o : out std_logic);-- ACAM IntFlag falling edge
stop_dis_o : out std_logic);
end acam_timecontrol_interface;
--=================================================================================================
-- architecture declaration
end entity;
--=================================================================================================
architecture rtl of acam_timecontrol_interface is
signal int_flag_synch, err_flag_synch : std_logic_vector(2 downto 0);
signal acam_intflag_f_edge_p : std_logic;
signal acam_intflag_f_edge_p, stop_dis_d1 : std_logic;
signal start_pulse, wait_for_utc, rst_n, wait_for_state_active : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
......@@ -120,30 +92,7 @@ begin
-- IntFlag and ERRflag Input Synchronizers --
---------------------------------------------------------------------------------------------------
rst_n <= not(rst_i);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
sync_err_flag: process (clk_i) -- synchronisation registers for ERR external signal
begin
if rising_edge (clk_i) then
if rst_i ='1' then
err_flag_synch <= (others => '0');
int_flag_synch <= (others => '0');
else
err_flag_synch <= err_flag_i & err_flag_synch(2 downto 1);
int_flag_synch <= int_flag_i & int_flag_synch(2 downto 1);
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
acam_errflag_f_edge_p_o <= not(err_flag_synch(1)) and err_flag_synch(0);
acam_errflag_r_edge_p_o <= err_flag_synch(1) and not(err_flag_synch(0));
acam_intflag_f_edge_p <= not(int_flag_synch(1)) and int_flag_synch(0);
acam_intflag_f_edge_p_o <= acam_intflag_f_edge_p;
rst_n <= not(rst_i);
---------------------------------------------------------------------------------------------------
-- start_from_fpga_o generation --
......@@ -152,36 +101,48 @@ begin
-- after the state_active_p_i (coming from the data_engine unit).
-- The pulse is synchronous to the utc_p_i
start_pulse_from_fpga: process (clk_i)
start_pulse_from_fpga : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' or deactivate_acq_p_i = '1' then
wait_for_utc <= '0';
start_pulse <= '0';
wait_for_state_active <= '0';
stop_dis_o <= '1';
else
if rst_i = '1' or deactivate_acq_p_i = '1' then
wait_for_utc <= '0';
start_pulse <= '0';
wait_for_state_active <= '0';
stop_dis_d1 <= '1';
else
if activate_acq_p_i = '1' then
wait_for_utc <= '1';
start_pulse <= '0';
wait_for_utc <= '1';
start_pulse <= '0';
elsif utc_p_i = '1' and wait_for_utc = '1' then
wait_for_utc <= '0';
start_pulse <= '1';
wait_for_state_active <= '1';
elsif wait_for_state_active = '1' and state_active_p_i = '1' then -- data_engine starts following ACAM EF
stop_dis_o <= '0';
wait_for_state_active <= '0';
else
start_pulse <= '0';
wait_for_state_active <= '1';
elsif wait_for_state_active = '1' and state_active_p_i = '1' then
-- data_engine starts following ACAM EF
stop_dis_d1 <= '0';
wait_for_state_active <= '0';
else
start_pulse <= '0';
end if;
end if;
end if;
end process;
stop_dis_extra_dff : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
stop_dis_o <= '1';
else
stop_dis_o <= stop_dis_d1;
end if;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
extend_pulse : gc_extend_pulse
generic map (g_width => 4)
port map
generic map (g_width => 4)
port map
(clk_i => clk_i,
rst_n_i => rst_n,
pulse_i => start_pulse,
......
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Channel registers
---------------------------------------------------------------------------------------
-- File : channel_regs.vhd
-- Author : auto-generated by wbgen2 from wbgen/channel_regs.wb
-- Created : Thu Sep 26 16:43:02 2019
-- Standard : VHDL'87