Commit 745e912c authored by Evangelia Gousiou's avatar Evangelia Gousiou

rollback to version before dlamprid commit (split channel CSR from FIFO readout)

parent 29c1fdd2
......@@ -395,28 +395,52 @@ begin
-- x5 FIFOS --
---------------------------------------------------------------------------------------------------
-- A FIFO with the timestamps of each channel
gen_enable_fifo_readout : if g_USE_FIFO_READOUT generate
gen_fifos : for i in 0 to 4 generate
U_TheFifo : entity work.timestamp_fifo
generic map (
g_USE_FIFO_READOUT => g_USE_FIFO_READOUT)
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_CHANNEL0 + i),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_CHANNEL0 + i),
irq_o => irq_fifo(i),
enable_i => channel_enable(i),
tick_i => tick_1ms,
irq_threshold_i => irq_threshold,
irq_timeout_i => irq_timeout,
timestamp_i => timestamp(i),
timestamp_valid_i => timestamp_stb(i),
ts_offset_o => ts_offset(i), -- to be used by the direct readout
reset_seq_o => reset_seq(i),
raw_enable_o => raw_enable(i));
timestamp_stb(i) <= tdc_timestamp_valid_p(i);
end generate gen_fifos;
generic map (
g_channel => i)
port map (
clk_sys_i => clk_sys_i,
rst_sys_n_i => rst_sys_n_i,
slave_i => cnx_master_out(c_WB_SLAVE_TDC_CHANNEL0 + i),
slave_o => cnx_master_in(c_WB_SLAVE_TDC_CHANNEL0 + i),
irq_o => irq_fifo(i),
enable_i => channel_enable(i),
tick_i => tick_1ms,
irq_threshold_i => irq_threshold,
irq_timeout_i => irq_timeout,
timestamp_i => timestamp,
timestamp_valid_i => timestamp_stb,
ts_offset_o => ts_offset(i),
reset_seq_o => reset_seq(i),
raw_enable_o => raw_enable(i));
timestamp_stb(i) <= tdc_timestamp_valid_p(i);
end generate gen_fifos;
end generate gen_enable_fifo_readout;
-- generic map (
-- g_USE_FIFO_READOUT => g_USE_FIFO_READOUT)
-- port map (
-- clk_sys_i => clk_sys_i,
-- rst_sys_n_i => rst_sys_n_i,
-- slave_i => cnx_master_out(c_WB_SLAVE_TDC_CHANNEL0 + i),
-- slave_o => cnx_master_in(c_WB_SLAVE_TDC_CHANNEL0 + i),
-- irq_o => irq_fifo(i),
-- enable_i => channel_enable(i),
-- tick_i => tick_1ms,
-- irq_threshold_i => irq_threshold,
-- irq_timeout_i => irq_timeout,
-- timestamp_i => timestamp(i),
-- timestamp_valid_i => timestamp_stb(i),
-- ts_offset_o => ts_offset(i), -- to be used by the direct readout
-- reset_seq_o => reset_seq(i),
-- raw_enable_o => raw_enable(i));
-- timestamp_stb(i) <= tdc_timestamp_valid_p(i);
-- end generate gen_fifos;
---------------------------------------------------------------------------------------------------
-- DMA --
......
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......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : timestamp_fifo_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/timestamp_fifo_wb.wb
-- Created : Thu Sep 26 16:42:08 2019
-- Created : Sun Sep 2 15:37:55 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/timestamp_fifo_wb.wb
......@@ -27,6 +27,10 @@ package tsf_wbgen2_pkg is
fifo_ts1_i : std_logic_vector(31 downto 0);
fifo_ts2_i : std_logic_vector(31 downto 0);
fifo_ts3_i : std_logic_vector(31 downto 0);
delta1_i : std_logic_vector(31 downto 0);
delta2_i : std_logic_vector(31 downto 0);
delta3_i : std_logic_vector(31 downto 0);
csr_delta_ready_i : std_logic;
end record;
constant c_tsf_in_registers_init_value: t_tsf_in_registers := (
......@@ -34,7 +38,11 @@ package tsf_wbgen2_pkg is
fifo_ts0_i => (others => '0'),
fifo_ts1_i => (others => '0'),
fifo_ts2_i => (others => '0'),
fifo_ts3_i => (others => '0')
fifo_ts3_i => (others => '0'),
delta1_i => (others => '0'),
delta2_i => (others => '0'),
delta3_i => (others => '0'),
csr_delta_ready_i => '0'
);
-- Output registers (WB slave -> user design)
......@@ -43,64 +51,82 @@ package tsf_wbgen2_pkg is
fifo_wr_full_o : std_logic;
fifo_wr_empty_o : std_logic;
fifo_wr_usedw_o : std_logic_vector(5 downto 0);
offset1_o : std_logic_vector(31 downto 0);
offset2_o : std_logic_vector(31 downto 0);
offset3_o : std_logic_vector(31 downto 0);
csr_delta_read_o : std_logic;
csr_rst_seq_o : std_logic;
csr_delta_ref_o : std_logic_vector(2 downto 0);
csr_raw_mode_o : std_logic;
end record;
constant c_tsf_out_registers_init_value: t_tsf_out_registers := (
fifo_wr_full_o => '0',
fifo_wr_empty_o => '0',
fifo_wr_usedw_o => (others => '0')
fifo_wr_usedw_o => (others => '0'),
offset1_o => (others => '0'),
offset2_o => (others => '0'),
offset3_o => (others => '0'),
csr_delta_read_o => '0',
csr_rst_seq_o => '0',
csr_delta_ref_o => (others => '0'),
csr_raw_mode_o => '0'
);
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component timestamp_fifo_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers
);
end component;
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component timestamp_fifo_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_tsf_in_registers;
regs_o : out t_tsf_out_registers
);
end component;
end package;
package body tsf_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = '1') then
tmp(i):= '1';
else
tmp(i):= '0';
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
variable tmp: t_tsf_in_registers;
begin
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
return tmp;
end function;
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_tsf_in_registers) return t_tsf_in_registers is
variable tmp: t_tsf_in_registers;
begin
tmp.fifo_wr_req_i := f_x_to_zero(left.fifo_wr_req_i) or f_x_to_zero(right.fifo_wr_req_i);
tmp.fifo_ts0_i := f_x_to_zero(left.fifo_ts0_i) or f_x_to_zero(right.fifo_ts0_i);
tmp.fifo_ts1_i := f_x_to_zero(left.fifo_ts1_i) or f_x_to_zero(right.fifo_ts1_i);
tmp.fifo_ts2_i := f_x_to_zero(left.fifo_ts2_i) or f_x_to_zero(right.fifo_ts2_i);
tmp.fifo_ts3_i := f_x_to_zero(left.fifo_ts3_i) or f_x_to_zero(right.fifo_ts3_i);
tmp.delta1_i := f_x_to_zero(left.delta1_i) or f_x_to_zero(right.delta1_i);
tmp.delta2_i := f_x_to_zero(left.delta2_i) or f_x_to_zero(right.delta2_i);
tmp.delta3_i := f_x_to_zero(left.delta3_i) or f_x_to_zero(right.delta3_i);
tmp.csr_delta_ready_i := f_x_to_zero(left.csr_delta_ready_i) or f_x_to_zero(right.csr_delta_ready_i);
return tmp;
end function;
end package body;
......@@ -6,8 +6,8 @@ package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:3fdaa92b28316925bd834b970aca201b4c4cd9cf" & LF
& "commit:29c1fdd2e474c7bdb52e11db26e94b502814290e" & LF
& "syntool:modelsim" & LF
& "syndate:2020-04-23, 00:03 CEST" & LF
& "syndate:2020-04-24, 17:39 CEST" & LF
& "synauth:Evangelia Gousiou" & LF;
end buildinfo_pkg;
......@@ -16,7 +16,6 @@
`define TDC_CORE_BASE 'h20000
`define TDC_CORE_CFG_BASE 'h2000
`define FIFO1_BASE 'h5000
`define FIFO1_BASE 'h5000
`define TDC_EIC_BASE 'h3000
`define TDC_DMA_BASE 'h6000
......@@ -100,16 +99,17 @@ class FmcTdcDriver;
task automatic update();
automatic uint32_t csr, t[4];
for(int i = 0; i < 1; i++) // only ch1 for now -- (int i = 0; i < 5; i++)
for(int i = 0; i < 1; i++) //(int i = 0; i < 5; i++)
begin
automatic uint32_t FIFObase = `FIFO1_BASE + i * 'h100;
automatic fmc_tdc_timestamp_t ts, ts1, ts2;
readl(FIFObase + `ADDR_TSF_FIFO_CSR, csr);
//$display("!!!csr %x: %x", FIFObase + `ADDR_TSF_FIFO_CSR, csr);
if( ! (csr & `TSF_FIFO_CSR_EMPTY ) )
//$display("FIFO has values");
begin
if( ! (csr & `TSF_FIFO_CSR_EMPTY ) ) begin
//$display("!!!FIFO not empty!!! csr %x; empty: %x", csr, `TSF_FIFO_CSR_EMPTY);
readl(FIFObase + `ADDR_TSF_FIFO_R0, t[0]);
readl(FIFObase + `ADDR_TSF_FIFO_R1, t[1]);
readl(FIFObase + `ADDR_TSF_FIFO_R2, t[2]);
......@@ -123,13 +123,14 @@ class FmcTdcDriver;
ts.channel = i;
m_queues[i].push_back(ts);
//$display("!!!Pushed in FIFO!!!");
end
end // for (int i = 0; i < 5; i++)
endtask // update_fifo
endtask // update
function int poll();
$display("[Info] m_queues[0].size: %d", m_queues[0].size());
return (m_queues[0].size() > 10);
//$display("[Info] m_queues[0].size: %d", m_queues[0].size());
return (m_queues[0].size() > 2);
endfunction // poll
function fmc_tdc_timestamp_t get();
......@@ -372,7 +373,7 @@ module main;
uint64_t d;
acc = Host.get_accessor();
#10us;
#5us;
// test read
acc.read('h2208c, d);
......
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