doc: fix memory maps

But still some improvements could be done... Signed-off-by: Adam Wujek <dev_public@wujek.eu>

doc: fix memory maps
But still some improvements could be done... Signed-off-by: Adam Wujek <dev_public@wujek.eu>
1ccf63d1 · Adam Wujek · 52f8bcba · 1ccf63d1 · 1ccf63d1 · 1ccf63d1
Commit 1ccf63d1 authored Mar 19, 2022 by Adam Wujek
8 changed files
--- a/doc/gateware/memory-map.rst
+++ b/doc/gateware/memory-map.rst
@@ -6,17 +6,6 @@
 The Memory Map
 ==============

-Following the memory map for the part of the TDC design that drives
-the FMC-TDC-1NS-5CH modules.
-
-.. only:: latex
-
-   .. warning::
-      Unfortunatelly we are not able to include the memory map in PDF format.
-      Please for the memory map refer to the online documentation,
-
-.. raw:: html
-   :file: regs/fmc_tdc_mezzanine_mmap.htm

 Supported Designs
 =================
@@ -30,3 +19,92 @@ registers and any other component used in an FMC-TDC-1NS-5CH design.

   spec_ref_fmc_tdc
   svec_ref_fmc_tdc
+
+.. _tdc_memory_map:
+
+TDC memory map
+==============
+
+Following the memory map for the part of the TDC design that drives
+the FMC-TDC-1NS-5CH modules.
+
+.. only:: latex
+
+   .. warning::
+      Unfortunately we are not able to include the memory map in PDF format.
+      Please for the memory map refer to the online documentation,
+
+.. raw:: html
+   :file: regs/fmc_tdc_mezzanine_mmap.htm
+
+One wire
+--------
+
+.. only:: latex
+
+   .. warning::
+      Unfortunately we are not able to include the memory map in PDF format.
+      Please for the memory map refer to the online documentation,
+
+.. raw:: html
+   :file: regs/tdc_onewire_wb.html
+
+Core
+----
+
+.. #note map not in wb nor cheby file
+
+EIC
+---
+
+
+.. only:: latex
+
+   .. warning::
+      Unfortunately we are not able to include the memory map in PDF format.
+      Please for the memory map refer to the online documentation,
+
+.. raw:: html
+   :file: regs/tdc_eic.html
+
+I2C
+---
+
+Not used.
+
+Mem
+---
+
+.. only:: latex
+
+   .. warning::
+      Unfortunately we are not able to include the memory map in PDF format.
+      Please for the memory map refer to the online documentation,
+
+.. raw:: html
+   :file: regs/timestamp_fifo_wb.html
+
+Mem DMA
+-------
+
+.. only:: latex
+
+   .. warning::
+      Unfortunately we are not able to include the memory map in PDF format.
+      Please for the memory map refer to the online documentation,
+
+.. raw:: html
+   :file: regs/tdc_buffer_control_regs.html
+
+Mem DMA EIC
+-----------
+
+.. only:: latex
+
+   .. warning::
+      Unfortunately we are not able to include the memory map in PDF format.
+      Please for the memory map refer to the online documentation,
+
+.. raw:: html
+   :file: regs/dma_eic.html
+
--- a/doc/gateware/regs/Makefile
+++ b/doc/gateware/regs/Makefile
@@ -10,11 +10,19 @@ HTML += svec_ref_fmc_tdc_mmap.htm
 HTML += spec_ref_fmc_tdc_mmap.htm
 HTML += fmc_tdc_mezzanine_mmap.htm

+HTML += dma_eic.html
+HTML += fmc_tdc_direct_readout_slave.html
+HTML += tdc_buffer_control_regs.html
+HTML += tdc_eic.html
+HTML += tdc_onewire_wb.html
+HTML += timestamp_fifo_wb.html
+
 all: $(HTML)

 .PHONY: clean

-CHEBY_BUILD=(cd $(dir $<); cheby -i $(notdir $<) --gen-doc --doc html) > $@
+CHEBY_BUILD=(cd $(dir $<); ~/.local/bin/cheby -i $(notdir $<) --gen-doc --doc html) > $@
+WBGEN2_BUILD=(wbgen2 -D $@ $<)

 fmc_tdc_mezzanine_mmap.htm: $(TOP_DIR)/hdl/cheby/fmc_tdc_mezzanine_mmap.cheby
 	$(CHEBY_BUILD)
@@ -31,5 +39,26 @@ svec_base_regs.htm: $(TOP_DIR)/hdl/ip_cores/svec/hdl/rtl/svec_base_regs.cheby
 spec_base_regs.htm: $(TOP_DIR)/hdl/ip_cores/spec/hdl/rtl/spec_base_regs.cheby
 	$(CHEBY_BUILD)

+timestamp_fifo_wb.html:            $(TOP_DIR)/hdl/rtl/wbgen/timestamp_fifo_wb.wb
+	$(WBGEN2_BUILD)
+
+dma_eic.html:                      $(TOP_DIR)/hdl/rtl/wbgen/dma_eic.wb
+	$(WBGEN2_BUILD)
+
+fmc_tdc_direct_readout_slave.html: $(TOP_DIR)/hdl/rtl/wbgen/fmc_tdc_direct_readout_slave.wb
+	$(WBGEN2_BUILD)
+
+tdc_buffer_control_regs.html:      $(TOP_DIR)/hdl/rtl/wbgen/tdc_buffer_control_regs.wb
+	$(WBGEN2_BUILD)
+
+tdc_eic.html:                      $(TOP_DIR)/hdl/rtl/wbgen/tdc_eic.wb
+	$(WBGEN2_BUILD)
+
+tdc_onewire_wb.html:               $(TOP_DIR)/hdl/rtl/wbgen/tdc_onewire_wb.wb
+	$(WBGEN2_BUILD)
+
+timestamp_fifo_wb.html:            $(TOP_DIR)/hdl/rtl/wbgen/timestamp_fifo_wb.wb
+	$(WBGEN2_BUILD)
+
 clean:
-	@rm -f *.md *.rst *.htm
+	@rm -f *.md *.rst *.htm *.html
--- a/doc/gateware/spec_ref_fmc_tdc.rst
+++ b/doc/gateware/spec_ref_fmc_tdc.rst
@@ -6,28 +6,37 @@
 SPEC FMC-TDC-1NS-5CHA
 =====================

-The memory map is divided in two parts: the `Carrier`_ part common to
-all SPEC designs, and the `FMC-TDC-1NS-5CHA`_ part specific to the
+The memory map is divided in two parts: the :ref:`Carrier (SPEC) <SPEC base regs>` part common to
+all SPEC designs, and the :ref:`TDC <TDC base regs>` part specific to the
 FMC-TDC-1NS-5CHA mezzanine.

-Carrier
-=======
 .. only:: latex

   .. warning::
-      Unfortunatelly we are not able to include the memory map in PDF format.
+      Unfortunately we are not able to include the memory map in PDF format.
      Please for the memory map refer to the online documentation,

 .. raw:: html
-   :file: regs/spec_base_regs.htm
+   :file: regs/spec_ref_fmc_tdc_mmap.htm
+
+.. _`SPEC base regs`:
+
+SPEC base registers
+===================

-FMC-TDC-1NS-5CHA
-================
 .. only:: latex

   .. warning::
-      Unfortunatelly we are not able to include the memory map in PDF format.
+      Unfortunately we are not able to include the memory map in PDF format.
      Please for the memory map refer to the online documentation,

 .. raw:: html
-   :file: regs/spec_ref_fmc_tdc_mmap.htm
+   :file: regs/spec_base_regs.htm
+
+
+.. _`TDC base regs`:
+
+FMC-TDC-1NS-5CHA
+================
+
+See :ref:`tdc_memory_map`.
--- a/doc/gateware/svec_ref_fmc_tdc.rst
+++ b/doc/gateware/svec_ref_fmc_tdc.rst
@@ -6,29 +6,46 @@
 SVEC FMC-TDC-1NS-5CHA
 =====================

-The memory map is divided in two parts: the `Carrier`_ part common to
-all SPEC designs, and the `FMC-TDC-1NS-5CHA`_ part specific to the
+The memory map is divided in two parts:
+the :ref:`Carrier (SVEC) <SVEC base regs>` part common to
+all SVEC designs, and two memory regions for TDCs
+(:ref:`TDC1 <TDC1 base regs>` and :ref:`TDC2 <TDC2 base regs>`) part specific to the
 FMC-TDC-1NS-5CHA mezzanine.

-Carrier
-=======
 .. only:: latex

   .. warning::
-      Unfortunatelly we are not able to include the memory map in PDF format.
+      Unfortunately we are not able to include the memory map in PDF format.
      Please for the memory map refer to the online documentation,

 .. raw:: html
-   :file: regs/svec_base_regs.htm
+   :file: regs/svec_ref_fmc_tdc_mmap.htm
+
+.. _`SVEC base regs`:

-FMC-TDC-1NS-5CHA
-================
+SVEC base registers
+===================

 .. only:: latex

   .. warning::
-      Unfortunatelly we are not able to include the memory map in PDF format.
+      Unfortunately we are not able to include the memory map in PDF format.
      Please for the memory map refer to the online documentation,

 .. raw:: html
-   :file: regs/svec_ref_fmc_tdc_mmap.htm
+   :file: regs/svec_base_regs.htm
+
+
+.. _`TDC1 base regs`:
+
+First FMC-TDC-1NS-5CHA
+======================
+
+See :ref:`tdc_memory_map`.
+
+.. _`TDC2 base regs`:
+
+Second FMC-TDC-1NS-5CHA
+=======================
+
+See :ref:`tdc_memory_map`.
--- a/doc/introduction.rst
+++ b/doc/introduction.rst
@@ -51,4 +51,4 @@ this license, visit http://creativecommons.org/licenses/by-sa/4.0/.
 .. _`FMC TDC 1ns 5 Channels`: https://ohwr.org/project/fmc-tdc
 .. _`Open HardWare Repository`: https://ohwr.org/
 .. _`Semantic Versioning`: https://semver.org/
-.. _`FPGA Release Page`: https://ohwr.org/project/fmc-tdc/wikis/Releases
+.. _`FPGA Bitstream Page`: https://ohwr.org/project/fmc-tdc/wikis/Releases
--- a/hdl/cheby/fmc_tdc_mezzanine_mmap.cheby
+++ b/hdl/cheby/fmc_tdc_mezzanine_mmap.cheby
@@ -6,4 +6,47 @@ memory-map:
  name: fmc_tdc_mezzanine_mmap
  bus: wb-32-be
  description: FMC-TDC-1NS-5CH mezzanine memory map
-  size: 0x2000
+  size: 0x8000
+  children:
+    - submap:
+        name: one-wire
+        description: One wire
+        address: 0x1000
+        size: 0x1000
+        interface: wb-32-be
+    - submap:
+        name: core
+        description: One wire
+        address: 0x2000
+        size: 0x1000
+        interface: wb-32-be
+    - submap:
+        name: eic
+        description: One wire
+        address: 0x3000
+        size: 0x1000
+        interface: wb-32-be
+    - submap:
+        name: i2c
+        description: One wire
+        address: 0x4000
+        size: 0x1000
+        interface: wb-32-be
+    - submap:
+        name: mem
+        description: One wire
+        address: 0x5000
+        size: 0x1000
+        interface: wb-32-be
+    - submap:
+        name: mem-dma
+        description: One wire
+        address: 0x6000
+        size: 0x1000
+        interface: wb-32-be
+    - submap:
+        name: mem-dma-eic
+        description: mem dma eic
+        address: 0x7000
+        size: 0x1000
+        interface: wb-32-be
--- a/hdl/cheby/spec_ref_fmc_tdc_mmap.cheby
+++ b/hdl/cheby/spec_ref_fmc_tdc_mmap.cheby
@@ -6,4 +6,17 @@ memory-map:
  name: spec_ref_fmc_tdc_mmap
  bus: wb-32-be
  description: SPEC FMC-TDC-1NS-5CHA memory map
-  size: 0x10000
\ No newline at end of file
+  size: 0x20000
+  children:
+    - submap:
+        name: spec-base-regs
+        description: spec-base-regs
+        address: 0x0
+        size: 0x2000
+        interface: wb-32-be
+    - submap:
+        name: tdc-base-regs
+        description: tdc-base-regs
+        address: 0x10000
+        size: 0x10000
+        interface: wb-32-be
--- a/hdl/cheby/svec_ref_fmc_tdc_mmap.cheby
+++ b/hdl/cheby/svec_ref_fmc_tdc_mmap.cheby
@@ -6,4 +6,23 @@ memory-map:
  name: svec_ref_fmc_tdc_mmap
  bus: wb-32-be
  description: SVEC FMC-TDC-1NS-5CHA memory map
-  size: 0x10000  
\ No newline at end of file
+  size: 0x30000  
+  children:
+    - submap:
+        name: svec-base-regs
+        description: svec-base-regs
+        address: 0x0
+        size: 0x10000
+        interface: wb-32-be
+    - submap:
+        name: tdc1-base-regs
+        description: tdc1-base-regs
+        address: 0x10000
+        size: 0x10000
+        interface: wb-32-be
+    - submap:
+        name: tdc2-base-regs
+        description: tdc2-base-regs
+        address: 0x20000
+        size: 0x10000
+        interface: wb-32-be