Commits · ee778274e69b753b2890d37f5d46d492af21eaa7 · Projects / FMC DEL 1ns 4cha · Open Hardware Repository

02 Dec, 2020 2 commits
- hdl/top: clean up legacy (pre-convention) toplevels · ee778274
  Tomasz Wlostowski authored Dec 02, 2020
  
  ee778274
- hdl: keep IODELAY adjustments in clk_ref clock domain, increase taps register length to 8 bits · 3b69f101
  Tomasz Wlostowski authored Dec 02, 2020
  
  3b69f101
08 Nov, 2020 1 commit
- Merge branch 'tom-spec-convention' into proposed_master · ecd0bb00
  Tomasz Wlostowski authored Nov 08, 2020
  
  ecd0bb00
23 Apr, 2020 1 commit
- wip commit · 32f77963
  Tomasz Wlostowski authored Apr 23, 2020
  
  32f77963
22 Oct, 2019 4 commits
- hdl: rename s[pv]ec_top to s[pv]ec_fine_delay_top for the clarity of build info data · 04f41501
  Tomasz Wlostowski authored Oct 22, 2019
  
  04f41501
- testbench: wip · 41d6ec31
  Tomasz Wlostowski authored Oct 22, 2019
  
  41d6ec31
- rtl: simple to use register for configuring the IODELAY tap number · 11309c73
  Tomasz Wlostowski authored Oct 22, 2019
  
  11309c73
- ip_cores: use latest general-cores... · 6e3fa544
  Tomasz Wlostowski authored Oct 22, 2019
  
  6e3fa544
15 Oct, 2019 2 commits
- rtl: expose g_fmc_slot_id parameter in component declaration · be2a5d7b
  Tomasz Wlostowski authored Oct 15, 2019
  
  be2a5d7b
- hdl: updated submodules · fbf84871
  Tomasz Wlostowski authored Oct 15, 2019
  
  fbf84871
11 Sep, 2019 5 commits
- syn/spec: ISE project for SPEC top level compliant with The Convention · 018715ac
  Tomasz Wlostowski authored Sep 11, 2019
  
  018715ac
- top/spec: SPEC top level compliant with The Convention · 6192e6db
  Tomasz Wlostowski authored Sep 11, 2019
  
  6192e6db
- rtl: added FMC_SLOT_ID register · b29188b3
  Tomasz Wlostowski authored Sep 11, 2019
  
  b29188b3
- rtl: tie unused int line · 4a39c5d8
  Tomasz Wlostowski authored Sep 11, 2019
  
  4a39c5d8
- hdl: updated submodules · 1a289f2c
  Tomasz Wlostowski authored Sep 11, 2019
  
  1a289f2c
01 Sep, 2019 2 commits
- wip · 40936f9e
  Tomasz Wlostowski authored Sep 01, 2019
  
  40936f9e
- updated submodules · 620cd691
  Tomasz Wlostowski authored Sep 01, 2019
  
  620cd691
02 Apr, 2019 6 commits
- syn: updated synthesis scripts for wrpc-v2.4 · 3c79319c
  Tomasz Wlostowski authored Apr 02, 2019
  
  3c79319c
- top/svec: IODELAY fix, migrated to wrpc v4-2 · 4a4b1152
  Tomasz Wlostowski authored Apr 02, 2019
  
  4a4b1152
- hdl: IODELAY control port in fine_delay_core · 99253dd6
  Tomasz Wlostowski authored Apr 02, 2019
  
  99253dd6
- hdl: added IODELAY control to the WB register block · f6a2b0a9
  Tomasz Wlostowski authored Apr 02, 2019
  
  f6a2b0a9
- hdl: don't sample start with the falling clock edge · 198cf18b
  Tomasz Wlostowski authored Apr 02, 2019
  
  198cf18b
- hdl: updated ip-cores to match wrpc v4.2 · 63e28db7
  Tomasz Wlostowski authored Apr 02, 2019
  
  63e28db7
17 Aug, 2018 1 commit
- hdl: use dual reset async fifos and pulse synchronizers to help with meeting timing · eca0894f
  Dimitris Lampridis authored Aug 17, 2018
  
  eca0894f
27 Jul, 2018 1 commit
- hdl: add root Manifest for easier integration into other projects · 84dca3f5
  Dimitris Lampridis authored Jul 27, 2018
  
  84dca3f5
20 Jul, 2018 1 commit
- hdl: eliminate WB int, bring all submodules up-to-date · 309cd51f
  Dimitris Lampridis authored Jul 20, 2018
  
  309cd51f
20 Mar, 2017 2 commits
- syn/spec: update Manifest.py for hdlmake v2.1 · 72f0b813
  Grzegorz Daniluk authored Mar 20, 2017
  
  72f0b813
- spec: update WRPC to v4.0 · 23700973
  Grzegorz Daniluk authored Mar 20, 2017
  
  23700973
02 Feb, 2015 1 commit
- circuit_board: synced with EDMS V6.1 release · 585895e2
  Tomasz Wlostowski authored Feb 02, 2015
  
  585895e2
09 Dec, 2014 3 commits
- top: updated to latest version of GN4124 core · a1af67a9
  Tomasz Wlostowski authored Dec 09, 2014
  
  a1af67a9
- hdl/ip_cores: updated submodules to latest versions (including WR Heisenbug fix) · e67d2ca1
  Tomasz Wlostowski authored Dec 09, 2014
  
  e67d2ca1
- doc/design-notes: minor fixes · c23f0572
  Tomasz Wlostowski authored Dec 09, 2014
  
  c23f0572
23 Sep, 2014 1 commit
- mechanical: heatsink design files · 7488357d
  Tomasz Wlostowski authored Sep 23, 2014
  
  7488357d
27 May, 2014 1 commit
- circuit_board: synced with EDMS V6.0 release · be77deff
  Tomasz Wlostowski authored May 27, 2014
  
  be77deff
26 Mar, 2014 1 commit
- hdl/top/spec: reduce fine '295 outputs drive strength on the SPEC too · 7dd0a8c3
  Tomasz Wlostowski authored Mar 26, 2014
  
  7dd0a8c3
25 Mar, 2014 3 commits
- hdl/syn/svec: migrate to ISE 14.5 · a3f676c4
  Tomasz Wlostowski authored Mar 25, 2014
  
  a3f676c4
- hdl/top/svec: reduce delay line control outputs drive stregths (fixes signal integrity issues) · cf1ce608
  Tomasz Wlostowski authored Mar 25, 2014
  
  cf1ce608
- hdl/rtl/fd_delay_line_arbiter.vhd: delay output by 1 cycle to improve timing closure · 6bf2c42b
  Tomasz Wlostowski authored Mar 25, 2014
  
  6bf2c42b
24 Mar, 2014 2 commits
- hdl/testbench/svec_wr_top: verify the new arbiter · 883c423a
  Tomasz Wlostowski authored Mar 24, 2014
  
  883c423a
- hdl/rtl/fd_delay_line_arbiter.vhd: rewritten for faster arbitration to never miss 600 ns deadline · 7dea47db
  Tomasz Wlostowski authored Mar 24, 2014
```
The commit also adds possibility of wiring the channel driver 0 and ACAM data valid strobes/state indication
to the front panel LEMO connectors on the SVEC carrier, for the purpose of debugging ACAM/output stage processing latency.
```
  7dea47db