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FMC DEL 1ns 4cha
Commit 32f77963 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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doc/design-notes/fd_main_regs.in
View file @ 32f77963
......@@ -125,19 +125,27 @@ Timestamp Buffer Debug Values Register
REG @tab
@code{TSBR_ADVANCE} @tab
Timestamp Buffer Advance Register
@item @code{0x7c} @tab
REG @tab
@code{FMC_SLOT_ID} @tab
FMC Slot ID Register
@item @code{0x80} @tab
REG @tab
@code{IODELAY_ADJ} @tab
I/O Delay Adjust Register
@item @code{0xa0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x84} @tab
@item @code{0xa4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x88} @tab
@item @code{0xa8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0x8c} @tab
@item @code{0xac} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
......@@ -359,21 +367,6 @@ Pulse <code>Alutrigger</code> line
@code{IDELAY_CE}
@tab @code{0} @tab
IDELAY CE (pulse)
@item @code{9}
@tab R/W @tab
@code{IDELAY_RST}
@tab @code{0} @tab
IDELAY RST (GPIO)
@item @code{10}
@tab R/W @tab
@code{IDELAY_CAL}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@item @code{11}
@tab R/W @tab
@code{IDELAY_INC}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -386,9 +379,6 @@ IDELAY CAL (GPIO)
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@item @code{IDELAY_CE} @tab Write 1 to pulse the IDELAY CE line for 1 clock tick.
@item @code{IDELAY_RST} @tab State of IDELAY RST line
@item @code{IDELAY_CAL} @tab State of IDELAY CAL line
@item @code{IDELAY_INC} @tab State of IDELAY INC line
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
......@@ -815,6 +805,26 @@ Debug value
@tab @code{0} @tab
Advance buffer readout
@end multitable
@regsection @code{FMC_SLOT_ID} - FMC Slot ID Register
Index of the hardware FMC slot the card is in.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{SLOT_ID}
@tab @code{X} @tab
Slot ID
@end multitable
@regsection @code{IODELAY_ADJ} - I/O Delay Adjust Register
Setup time adjust for certain signals (e.g. TDC_START).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{5...0}
@tab R/W @tab
@code{N_TAPS}
@tab @code{X} @tab
Number of delay line taps.
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
......
gn4124-core @ 91d5efac
Subproject commit 254c6ef95db36035b80917eeeb26552b40d8edd1
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
spec @ 7911a138
Subproject commit 13afc71072f38174e9f738c081cdb4fdc82a07dc
Subproject commit 7911a1387bd47bc74e52957509ba7f303b5880b8
hdl/syn/spec/Manifest.py
View file @ 32f77963
......@@ -9,11 +9,11 @@ if locals().get('fetchto', None) is None:
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_fine_delay.xise"
syn_project = "spec_fine_delay_top.xise"
syn_tool = "ise"
syn_top = "spec_fine_delay_top"
spec_template_ucf = ['wr', 'onewire', 'spi']
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
......
hdl/syn/spec/spec_fine_delay.xise deleted 100644 → 0
View file @ 04f41501
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hdl/syn/svec/svec_fine_delay.xise
View file @ 32f77963
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hdl/top/spec/Manifest.py
View file @ 32f77963
......@@ -10,6 +10,7 @@ modules = {
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/gn4124-core",
"../../ip_cores/spec"
"../../ip_cores/spec",
"../../ip_cores/ddr3-sp6-core"
]
}
hdl/top/spec/spec_fine_delay_top.vhd
View file @ 32f77963
......@@ -4,7 +4,7 @@
-- https://ohwr.org/projects/fmc-delay-1ns-8cha
--------------------------------------------------------------------------------
--
-- unit name: spec_top
-- unit name: spec_fine_delay_top
--
-- description: Top entity for Fine Delay reference design.
--
......@@ -35,7 +35,10 @@ use work.wr_board_pkg.all;
use work.wr_fabric_pkg.all;
use work.fine_delay_pkg.all;
entity spec_top is
library unisim;
use unisim.vcomponents.all;
entity spec_fine_delay_top is
generic (
g_WRPC_INITF : string := "../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
......@@ -174,9 +177,9 @@ entity spec_top is
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic);
end entity spec_top;
end entity spec_fine_delay_top;
architecture arch of spec_top is
architecture arch of spec_fine_delay_top is
component IBUFDS is
......@@ -288,14 +291,20 @@ architecture arch of spec_top is
signal fmc0_fd_owr_en : std_logic;
signal fmc0_fd_owr_in : std_logic;
signal fmc0_fd_tdc_start_predelay : std_logic;
signal fmc0_tdc_start_iodelay_inc : std_logic;
signal fmc0_tdc_start_iodelay_rst : std_logic;
signal fmc0_tdc_start_iodelay_cal : std_logic;
signal fmc0_tdc_start_iodelay_ce : std_logic;
begin -- architecture arch
cmp_xwb_metadata : entity work.xwb_metadata
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => x"574E_cafe", -- WRTD Node (WN) 1
g_DEVICE_ID => x"574f_0001", -- SPEC + 1xFine Delay
g_VERSION => x"0100_0000",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
......@@ -305,7 +314,7 @@ begin -- architecture arch
wb_i => cnx_slave_in(c_WB_SLAVE_METADATA),
wb_o => cnx_slave_out(c_WB_SLAVE_METADATA));
inst_spec_template : entity work.spec_template_wr
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
......@@ -315,8 +324,9 @@ begin -- architecture arch
g_APP_OFFSET => c_METADATA_ADDR,
g_NUM_USER_IRQ => 5,
g_DPRAM_INITF => g_WRPC_INITF,
g_AUX_CLKS => 1,
g_FABRIC_IFACE => plain,
g_SIMULATION => g_SIMULATION)
g_SIMULATION => f_int2bool(g_SIMULATION))
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
......@@ -353,7 +363,7 @@ begin -- architecture arch
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_i => button1_n_i,
button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
......@@ -375,10 +385,10 @@ begin -- architecture arch
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
clk_dmtd_125m_o => clk_dmtd_125m,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => rst_ref_125m_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
clk_125m_ref_o => clk_ref_125m,
rst_125m_ref_n_o => rst_ref_125m_n,
irq_user_i => irq_vector,
tm_link_up_o => tm_link_up,
tm_time_valid_o => tm_time_valid,
......@@ -388,9 +398,6 @@ begin -- architecture arch
pps_p_o => open,
pps_led_o => pps_led,
link_ok_o => wrabbit_en,
ddr_dma_clk_i => '0',
ddr_dma_rst_n_i => '0',
ddr_dma_wb_i => c_DUMMY_WB_SLAVE_D64_IN,
app_wb_o => cnx_master_out(c_WB_MASTER_GENNUM),
app_wb_i => cnx_master_in(c_WB_MASTER_GENNUM));
......@@ -438,11 +445,31 @@ begin -- architecture arch
IBUF_LOW_PWR => false -- Low power (TRUE) vs. performance (FALSE) setting for referenced
)
port map (
O => fmc0_fd_tdc_start, -- Buffer output
O => fmc0_fd_tdc_start_predelay, -- Buffer output
I => fmc0_fd_tdc_start_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => fmc0_fd_tdc_start_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_fd_tdc_start_delay0 : IODELAY2
generic map (
DELAY_SRC => "IDATAIN",
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
DATA_RATE => "SDR"
)
port map (
IDATAIN => fmc0_fd_tdc_start_predelay,
DATAOUT2 => fmc0_fd_tdc_start,
INC => fmc0_tdc_start_iodelay_inc,
CE => fmc0_tdc_start_iodelay_ce,
RST => fmc0_tdc_start_iodelay_rst,
CLK => clk_sys_62m5,
ODATAIN => '0',
CAL => fmc0_tdc_start_iodelay_cal,
T => '1',
IOCLK0 => fmc0_dcm_clk_ref_0,
IOCLK1 => '0'
);
cmp0_fd_ddr_pll : entity work.fd_ddr_pll
port map (
RST => fmc0_ddr_pll_reset,
......@@ -473,6 +500,11 @@ begin -- architecture arch
dcm_reset_o => open,
dcm_locked_i => fmc0_ddr_pll_locked,
idelay_cal_o => fmc0_tdc_start_iodelay_cal,
idelay_rst_o => fmc0_tdc_start_iodelay_rst,
idelay_ce_o => fmc0_tdc_start_iodelay_ce,
idelay_inc_o => fmc0_tdc_start_iodelay_inc,
trig_a_i => fmc0_fd_trig_a_i,
tdc_cal_pulse_o => fmc0_fd_tdc_cal_pulse_o,
tdc_start_i => fmc0_fd_tdc_start,
......
hdl/top/svec/Manifest.py
View file @ 32f77963
......@@ -11,5 +11,6 @@ modules = {
"../../ip_cores/wr-cores/board/svec",
"../../ip_cores/vme64x-core",
"../../ip_cores/svec",
"../../ip_cores/ddr3-sp6-core",
]
}
hdl/top/svec/svec_file_delay_top.vhd deleted 100644 → 0
View file @ 04f41501
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