Commit 40936f9e authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

wip

parent 620cd691
......@@ -354,6 +354,26 @@ Stop disable
@code{ALUTRIG}
@tab @code{0} @tab
Pulse <code>Alutrigger</code> line
@item @code{8}
@tab W/O @tab
@code{IDELAY_CE}
@tab @code{0} @tab
IDELAY CE (pulse)
@item @code{9}
@tab R/W @tab
@code{IDELAY_RST}
@tab @code{0} @tab
IDELAY RST (GPIO)
@item @code{10}
@tab R/W @tab
@code{IDELAY_CAL}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@item @code{11}
@tab R/W @tab
@code{IDELAY_INC}
@tab @code{0} @tab
IDELAY CAL (GPIO)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -365,6 +385,10 @@ Pulse <code>Alutrigger</code> line
@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@item @code{IDELAY_CE} @tab Write 1 to pulse the IDELAY CE line for 1 clock tick.
@item @code{IDELAY_RST} @tab State of IDELAY RST line
@item @code{IDELAY_CAL} @tab State of IDELAY CAL line
@item @code{IDELAY_INC} @tab State of IDELAY INC line
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
......
`timescale 10fs/10fs
module jittery_delay
(
......@@ -20,4 +21,4 @@ module jittery_delay
out_o <= #(delta) in_i;
end
endmodule // jittery_delay
\ No newline at end of file
endmodule // jittery_delay
......@@ -12,7 +12,7 @@
`define FD_GCR_INPUT_EN_OFFSET 1
`define FD_GCR_INPUT_EN 32'h00000002
`define FD_GCR_DDR_LOCKED_OFFSET 2
`define FD_GCR_DDR_LOCKED 32'h00000004
`define FD_GCR_DDR_LOCKED 32'h0000CAL0004
`define FD_GCR_FMC_PRESENT_OFFSET 3
`define FD_GCR_FMC_PRESENT 32'h00000008
`define ADDR_FD_TCR 8'hc
......@@ -53,6 +53,14 @@
`define FD_TDCSR_STOP_DIS 32'h00000040
`define FD_TDCSR_ALUTRIG_OFFSET 7
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define FD_TDCSR_IDELAY_RST_OFFSET 9
`define FD_TDCSR_IDELAY_RST 32'h00000200
`define FD_TDCSR_IDELAY_CAL_OFFSET 10
`define FD_TDCSR_IDELAY_CAL 32'h00000400
`define FD_TDCSR_IDELAY_INC_OFFSET 11
`define FD_TDCSR_IDELAY_INC 32'h00000800
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......
......@@ -10,8 +10,8 @@ module tunable_clock_gen
parameter g_tunable = 0;
parameter g_tuning_range = 20e-6; // 20 ppm
parameter g_tuning_voltage = 1.0;
parameter real g_period = 8ns;
parameter real g_jitter = 10ps;
parameter time g_period = 8ns;
parameter time g_jitter = 10ps;
reg clk = 1'b1;
......@@ -74,4 +74,4 @@ module tunable_clock_gen
end // else: !if(enable)
assign clk_o = clk;
endmodule // tunable_clock_gen
\ No newline at end of file
endmodule // tunable_clock_gen
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include"
sim_tool="modelsim"
sim_top="main"
include_dirs = ["../../include/wb", "../../include/vme64x_bfm", "../../include" ];
syn_device="xc6slx150t"
files = [ "main.sv" ]
......
......@@ -182,6 +182,8 @@ module main;
drv0 = new(acc, 'h80010000);
drv0.init();
drv0.set_idelay_taps(30);
t_start=new;
drv0.get_time(t_start);
t_start.coarse += 20000;
......
vlog -sv main.sv +incdir+. +incdir+../../include/wb +incdir+../../include/vme64x_bfm +incdir+../../include
vsim work.main -voptargs=+acc
vsim -t 1ps work.main -novopt -L unisim
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
......@@ -39,6 +39,33 @@ class CSimDrv_FineDelay;
endfunction // new
task set_idelay_taps( int taps );
uint64_t tdcsr;
readl(`ADDR_FD_TDCSR, tdcsr);
// calibrate the iodelay
writel( `ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CAL );
#3us;
writel( `ADDR_FD_TDCSR , tdcsr );
$display("Set IDELAY tap count = %d", taps);
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_RST );
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_INC );
for(int i = 0; i<taps;i++)
begin
writel(`ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CE | `FD_TDCSR_IDELAY_INC );
#1us;
end
endtask // set_idelay_taps
/* fixme - maybe use real mcp23s17 model instead of this stub? */
task sgpio_write(int value);
......
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