Skip to content

F
FMC DEL 1ns 4cha
Commit 41d6ec31 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
Browse files
Options

testbench: wip

parent 11309c73
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 245 additions and 255 deletions
hdl/include/regs/fd_main_regs.vh
View file @ 41d6ec31
......@@ -12,7 +12,7 @@
`define FD_GCR_INPUT_EN_OFFSET 1
`define FD_GCR_INPUT_EN 32'h00000002
`define FD_GCR_DDR_LOCKED_OFFSET 2
`define FD_GCR_DDR_LOCKED 32'h0000CAL0004
`define FD_GCR_DDR_LOCKED 32'h00000004
`define FD_GCR_FMC_PRESENT_OFFSET 3
`define FD_GCR_FMC_PRESENT 32'h00000008
`define ADDR_FD_TCR 8'hc
......@@ -55,12 +55,6 @@
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define FD_TDCSR_IDELAY_RST_OFFSET 9
`define FD_TDCSR_IDELAY_RST 32'h00000200
`define FD_TDCSR_IDELAY_CAL_OFFSET 10
`define FD_TDCSR_IDELAY_CAL 32'h00000400
`define FD_TDCSR_IDELAY_INC_OFFSET 11
`define FD_TDCSR_IDELAY_INC 32'h00000800
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......@@ -163,28 +157,34 @@
`define ADDR_FD_TSBR_ADVANCE 8'h78
`define FD_TSBR_ADVANCE_ADV_OFFSET 0
`define FD_TSBR_ADVANCE_ADV 32'h00000001
`define ADDR_FD_EIC_IDR 8'h80
`define ADDR_FD_FMC_SLOT_ID 8'h7c
`define FD_FMC_SLOT_ID_SLOT_ID_OFFSET 0
`define FD_FMC_SLOT_ID_SLOT_ID 32'h0000000f
`define ADDR_FD_IODELAY_ADJ 8'h80
`define FD_IODELAY_ADJ_N_TAPS_OFFSET 0
`define FD_IODELAY_ADJ_N_TAPS 32'h0000003f
`define ADDR_FD_EIC_IDR 8'ha0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IDR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IDR_DMTD_SPLL 32'h00000002
`define FD_EIC_IDR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IDR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IER 8'h84
`define ADDR_FD_EIC_IER 8'ha4
`define FD_EIC_IER_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IER_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IER_DMTD_SPLL_OFFSET 1
`define FD_EIC_IER_DMTD_SPLL 32'h00000002
`define FD_EIC_IER_SYNC_STATUS_OFFSET 2
`define FD_EIC_IER_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IMR 8'h88
`define ADDR_FD_EIC_IMR 8'ha8
`define FD_EIC_IMR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IMR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IMR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IMR_DMTD_SPLL 32'h00000002
`define FD_EIC_IMR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IMR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_ISR 8'h8c
`define ADDR_FD_EIC_ISR 8'hac
`define FD_EIC_ISR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_ISR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_ISR_DMTD_SPLL_OFFSET 1
......
hdl/include/vme64x_bfm/svec_vme_buffers.svh
View file @ 41d6ec31
......@@ -162,6 +162,16 @@ function automatic bit[5:0] _gen_ga(int slot);
return {^slot_id, ~slot_id};
endfunction // _gen_ga
function automatic bit[4:0] _gen_ga_convention(int slot);
bit[4:0] slot_id = slot;
return {~slot_id};
endfunction // _gen_ga
function automatic bit _gen_gap_convention(int slot);
bit[4:0] slot_id = slot;
return ^slot_id;
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
......@@ -190,4 +200,30 @@ endfunction // _gen_ga
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
\ No newline at end of file
`define WIRE_VME_PINS_CONVENTION(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_SYSRESET_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga_convention(slot_id)),\
.VME_GAP_i(_gen_gap_convention(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_IRQ_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
hdl/testbench/svec_wr_top/Manifest.py
View file @ 41d6ec31
ctrls = ["bank3_32b_32b"]
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
sim_tool="modelsim"
sim_top="main"
include_dirs = ["../../include/vme64x_bfm",
"../../include/wb", "../../include",
"../../ip_cores/general-cores/modules/wishbone/wb_spi/",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/"]
syn_device = "xc6slx45t"
sim_tool = "modelsim"
sim_top = "main"
top_module = "main"
files = ["main.sv","buildinfo_pkg.vhd"]
include_dirs = ["../../include/wb", "../../include/vme64x_bfm", "../../include" ];
syn_device="xc6slx150t"
files = [ "main.sv" ]
modules = { "local" : [ "../../top/svec" ] }
modules = {"local": ["../../top/svec" ]}
#try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
#except:
# pass
hdl/testbench/svec_wr_top/fdelay_board.svh
View file @ 41d6ec31
......@@ -223,34 +223,34 @@ module fdelay_board (
endmodule // main
`define WIRE_FINE_DELAY_PINS(fmc_index,iface) \
.fd``fmc_index``_tdc_start_p_i (iface.core.tdc_start_p), \
.fd``fmc_index``_tdc_start_n_i (iface.core.tdc_start_n), \
.fd``fmc_index``_clk_ref_p_i (iface.core.clk_ref_p), \
.fd``fmc_index``_clk_ref_n_i (iface.core.clk_ref_n), \
.fd``fmc_index``_trig_a_i (iface.core.trig_a), \
.fd``fmc_index``_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fd``fmc_index``_tdc_d_b (iface.core.tdc_d), \
.fd``fmc_index``_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fd``fmc_index``_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fd``fmc_index``_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fd``fmc_index``_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fd``fmc_index``_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fd``fmc_index``_led_trig_o (iface.core.led_trig), \
.fd``fmc_index``_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fd``fmc_index``_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fd``fmc_index``_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fd``fmc_index``_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fd``fmc_index``_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fd``fmc_index``_spi_sclk_o (iface.core.spi_sclk), \
.fd``fmc_index``_spi_mosi_o (iface.core.spi_mosi), \
.fd``fmc_index``_spi_miso_i (iface.core.spi_miso), \
.fd``fmc_index``_delay_len_o (iface.core.delay_len), \
.fd``fmc_index``_delay_val_o (iface.core.delay_val), \
.fd``fmc_index``_delay_pulse_o (iface.core.delay_pulse), \
.fd``fmc_index``_dmtd_clk_o (iface.core.dmtd_clk), \
.fd``fmc_index``_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fd``fmc_index``_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fd``fmc_index``_pll_status_i (iface.core.pll_status), \
.fd``fmc_index``_ext_rst_n_o (iface.core.ext_rst_n), \
.fd``fmc_index``_onewire_b (iface.core.onewire)
.fmc``fmc_index``_fd_tdc_start_p_i (iface.core.tdc_start_p), \
.fmc``fmc_index``_fd_tdc_start_n_i (iface.core.tdc_start_n), \
.fmc``fmc_index``_fd_clk_ref_p_i (iface.core.clk_ref_p), \
.fmc``fmc_index``_fd_clk_ref_n_i (iface.core.clk_ref_n), \
.fmc``fmc_index``_fd_trig_a_i (iface.core.trig_a), \
.fmc``fmc_index``_fd_tdc_cal_pulse_o (iface.core.tdc_cal_pulse), \
.fmc``fmc_index``_fd_tdc_d_b (iface.core.tdc_d), \
.fmc``fmc_index``_fd_tdc_emptyf_i (iface.core.tdc_emptyf), \
.fmc``fmc_index``_fd_tdc_alutrigger_o (iface.core.tdc_alutrigger), \
.fmc``fmc_index``_fd_tdc_wr_n_o (iface.core.tdc_wr_n), \
.fmc``fmc_index``_fd_tdc_rd_n_o (iface.core.tdc_rd_n), \
.fmc``fmc_index``_fd_tdc_oe_n_o (iface.core.tdc_oe_n), \
.fmc``fmc_index``_fd_led_trig_o (iface.core.led_trig), \
.fmc``fmc_index``_fd_tdc_start_dis_o (iface.core.tdc_start_dis), \
.fmc``fmc_index``_fd_tdc_stop_dis_o (iface.core.tdc_stop_dis), \
.fmc``fmc_index``_fd_spi_cs_dac_n_o (iface.core.spi_cs_dac_n), \
.fmc``fmc_index``_fd_spi_cs_pll_n_o (iface.core.spi_cs_pll_n), \
.fmc``fmc_index``_fd_spi_cs_gpio_n_o (iface.core.spi_cs_gpio_n), \
.fmc``fmc_index``_fd_spi_sclk_o (iface.core.spi_sclk), \
.fmc``fmc_index``_fd_spi_mosi_o (iface.core.spi_mosi), \
.fmc``fmc_index``_fd_spi_miso_i (iface.core.spi_miso), \
.fmc``fmc_index``_fd_delay_len_o (iface.core.delay_len), \
.fmc``fmc_index``_fd_delay_val_o (iface.core.delay_val), \
.fmc``fmc_index``_fd_delay_pulse_o (iface.core.delay_pulse), \
.fmc``fmc_index``_fd_dmtd_clk_o (iface.core.dmtd_clk), \
.fmc``fmc_index``_fd_dmtd_fb_in_i (iface.core.dmtd_fb_in), \
.fmc``fmc_index``_fd_dmtd_fb_out_i (iface.core.dmtd_fb_out), \
.fmc``fmc_index``_fd_pll_status_i (iface.core.pll_status), \
.fmc``fmc_index``_fd_ext_rst_n_o (iface.core.ext_rst_n), \
.fmc``fmc_index``_fd_onewire_b (iface.core.onewire)
hdl/testbench/svec_wr_top/main.sv
View file @ 41d6ec31
......@@ -105,7 +105,6 @@ module main;
`DECLARE_VME_BUFFERS(VME.slave);
svec_top #(
.g_with_wr_phy(0),
.g_simulation(1)
) DUT (
.clk_125m_pllref_p_i(clk_125m),
......@@ -116,7 +115,7 @@ module main;
.rst_n_i(rst_n),
`WIRE_VME_PINS(8),
`WIRE_VME_PINS_CONVENTION(8),
`WIRE_FINE_DELAY_PINS(0, I_fmc0),
`WIRE_FINE_DELAY_PINS(1, I_fmc1)
);
......@@ -169,6 +168,7 @@ module main;
Timestamp dly, t_start;
CSimDrv_FineDelay drv0;
CSimDrv_FineDelay drv1;
uint64_t d;
#20us;
......@@ -181,17 +181,19 @@ module main;
drv0 = new(acc, 'h80010000);
drv0.init();
drv1 = new(acc, 'h80020000);
drv1.init();
drv0.set_idelay_taps(30);
drv0.set_idelay_taps(5);
t_start=new;
/* t_start=new;
drv0.get_time(t_start);
t_start.coarse += 20000;
drv0.config_output(0, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001000, -1);
drv0.config_output(1, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001100, -1);
drv0.config_output(2, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001200, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1);
drv0.config_output(3, CSimDrv_FineDelay::PULSE_GEN, 1, t_start, 200000, 1001300, -1); */
$display("Init done");
......
hdl/testbench/svec_wr_top/simdrv_fine_delay.svh
View file @ 41d6ec31
......@@ -42,26 +42,10 @@ class CSimDrv_FineDelay;
task set_idelay_taps( int taps );
uint64_t tdcsr;
readl(`ADDR_FD_TDCSR, tdcsr);
// calibrate the iodelay
writel( `ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CAL );
#3us;
writel( `ADDR_FD_TDCSR , tdcsr );
$display("Set IDELAY tap count = %d", taps);
$display("Set Idelay taps : %d\n", taps);
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_RST );
writel( `ADDR_FD_TDCSR, tdcsr | `FD_TDCSR_IDELAY_INC );
for(int i = 0; i<taps;i++)
begin
writel(`ADDR_FD_TDCSR , tdcsr | `FD_TDCSR_IDELAY_CE | `FD_TDCSR_IDELAY_INC );
#1us;
end
writel(`ADDR_FD_IODELAY_ADJ, taps);
endtask // set_idelay_taps
......
hdl/testbench/svec_wr_top/wave.do
View file @ 41d6ec31
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment