Commit ecd0bb00 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

Merge branch 'tom-spec-convention' into proposed_master

parents eca0894f 32f77963
[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
url = https://ohwr.org/project/general-cores.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = git://ohwr.org/hdl-core-lib/wr-cores.git
url = https://ohwr.org/project/wr-cores.git
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = git://ohwr.org/hdl-core-lib/vme64x-core.git
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
url = https://ohwr.org/project/gn4124-core.git
[submodule "hdl/ip_cores/spec"]
path = hdl/ip_cores/spec
url = https://ohwr.org/project/spec.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = https://ohwr.org/project/ddr3-sp6-core.git
[submodule "vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/svec"]
path = hdl/ip_cores/svec
url = https://ohwr.org/project/svec.git
......@@ -125,19 +125,27 @@ Timestamp Buffer Debug Values Register
REG @tab
@code{TSBR_ADVANCE} @tab
Timestamp Buffer Advance Register
@item @code{0x7c} @tab
REG @tab
@code{FMC_SLOT_ID} @tab
FMC Slot ID Register
@item @code{0x80} @tab
REG @tab
@code{IODELAY_ADJ} @tab
I/O Delay Adjust Register
@item @code{0xa0} @tab
REG @tab
@code{EIC_IDR} @tab
Interrupt disable register
@item @code{0x84} @tab
@item @code{0xa4} @tab
REG @tab
@code{EIC_IER} @tab
Interrupt enable register
@item @code{0x88} @tab
@item @code{0xa8} @tab
REG @tab
@code{EIC_IMR} @tab
Interrupt mask register
@item @code{0x8c} @tab
@item @code{0xac} @tab
REG @tab
@code{EIC_ISR} @tab
Interrupt status register
......@@ -354,6 +362,11 @@ Stop disable
@code{ALUTRIG}
@tab @code{0} @tab
Pulse <code>Alutrigger</code> line
@item @code{8}
@tab W/O @tab
@code{IDELAY_CE}
@tab @code{0} @tab
IDELAY CE (pulse)
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -365,6 +378,7 @@ Pulse <code>Alutrigger</code> line
@item @code{START_EN} @tab Controls the @code{StartDis} input of the TDC.@* write 1: enables the TDC start input.@* write 0: no effect.
@item @code{STOP_DIS} @tab Controls the @code{StopDis} input of the TDC.@* write 1: disables the TDC stop input.@* write 0: no effect.
@item @code{ALUTRIG} @tab Controls the TDC's @code{Alutrigger} line. Depending on the TDC's configuration, it can be used as a reset/FIFO clear/trigger signal.@* write 1: generates a pulse ACAM's @code{Alutrigger} line@* write 0: no effect.
@item @code{IDELAY_CE} @tab Write 1 to pulse the IDELAY CE line for 1 clock tick.
@end multitable
@regsection @code{CALR} - Calibration register
Controls calibration logic.
......@@ -791,6 +805,26 @@ Debug value
@tab @code{0} @tab
Advance buffer readout
@end multitable
@regsection @code{FMC_SLOT_ID} - FMC Slot ID Register
Index of the hardware FMC slot the card is in.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{3...0}
@tab R/O @tab
@code{SLOT_ID}
@tab @code{X} @tab
Slot ID
@end multitable
@regsection @code{IODELAY_ADJ} - I/O Delay Adjust Register
Setup time adjust for certain signals (e.g. TDC_START).
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{5...0}
@tab R/W @tab
@code{N_TAPS}
@tab @code{X} @tab
Number of delay line taps.
@end multitable
@regsection @code{EIC_IDR} - Interrupt disable register
Writing 1 disables handling of the interrupt associated with corresponding bit. Writin 0 has no effect.
@multitable @columnfractions .10 .10 .15 .10 .55
......
`timescale 10fs/10fs
module jittery_delay
(
......@@ -20,4 +21,4 @@ module jittery_delay
out_o <= #(delta) in_i;
end
endmodule // jittery_delay
\ No newline at end of file
endmodule // jittery_delay
......@@ -53,6 +53,8 @@
`define FD_TDCSR_STOP_DIS 32'h00000040
`define FD_TDCSR_ALUTRIG_OFFSET 7
`define FD_TDCSR_ALUTRIG 32'h00000080
`define FD_TDCSR_IDELAY_CE_OFFSET 8
`define FD_TDCSR_IDELAY_CE 32'h00000100
`define ADDR_FD_CALR 8'h24
`define FD_CALR_CAL_PULSE_OFFSET 0
`define FD_CALR_CAL_PULSE 32'h00000001
......@@ -155,28 +157,34 @@
`define ADDR_FD_TSBR_ADVANCE 8'h78
`define FD_TSBR_ADVANCE_ADV_OFFSET 0
`define FD_TSBR_ADVANCE_ADV 32'h00000001
`define ADDR_FD_EIC_IDR 8'h80
`define ADDR_FD_FMC_SLOT_ID 8'h7c
`define FD_FMC_SLOT_ID_SLOT_ID_OFFSET 0
`define FD_FMC_SLOT_ID_SLOT_ID 32'h0000000f
`define ADDR_FD_IODELAY_ADJ 8'h80
`define FD_IODELAY_ADJ_N_TAPS_OFFSET 0
`define FD_IODELAY_ADJ_N_TAPS 32'h0000003f
`define ADDR_FD_EIC_IDR 8'ha0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IDR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IDR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IDR_DMTD_SPLL 32'h00000002
`define FD_EIC_IDR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IDR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IER 8'h84
`define ADDR_FD_EIC_IER 8'ha4
`define FD_EIC_IER_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IER_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IER_DMTD_SPLL_OFFSET 1
`define FD_EIC_IER_DMTD_SPLL 32'h00000002
`define FD_EIC_IER_SYNC_STATUS_OFFSET 2
`define FD_EIC_IER_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_IMR 8'h88
`define ADDR_FD_EIC_IMR 8'ha8
`define FD_EIC_IMR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_IMR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_IMR_DMTD_SPLL_OFFSET 1
`define FD_EIC_IMR_DMTD_SPLL 32'h00000002
`define FD_EIC_IMR_SYNC_STATUS_OFFSET 2
`define FD_EIC_IMR_SYNC_STATUS 32'h00000004
`define ADDR_FD_EIC_ISR 8'h8c
`define ADDR_FD_EIC_ISR 8'hac
`define FD_EIC_ISR_TS_BUF_NOTEMPTY_OFFSET 0
`define FD_EIC_ISR_TS_BUF_NOTEMPTY 32'h00000001
`define FD_EIC_ISR_DMTD_SPLL_OFFSET 1
......
......@@ -10,8 +10,8 @@ module tunable_clock_gen
parameter g_tunable = 0;
parameter g_tuning_range = 20e-6; // 20 ppm
parameter g_tuning_voltage = 1.0;
parameter real g_period = 8ns;
parameter real g_jitter = 10ps;
parameter time g_period = 8ns;
parameter time g_jitter = 10ps;
reg clk = 1'b1;
......@@ -74,4 +74,4 @@ module tunable_clock_gen
end // else: !if(enable)
assign clk_o = clk;
endmodule // tunable_clock_gen
\ No newline at end of file
endmodule // tunable_clock_gen
......@@ -162,6 +162,16 @@ function automatic bit[5:0] _gen_ga(int slot);
return {^slot_id, ~slot_id};
endfunction // _gen_ga
function automatic bit[4:0] _gen_ga_convention(int slot);
bit[4:0] slot_id = slot;
return {~slot_id};
endfunction // _gen_ga
function automatic bit _gen_gap_convention(int slot);
bit[4:0] slot_id = slot;
return ^slot_id;
endfunction // _gen_ga
`define WIRE_VME_PINS(slot_id) \
......@@ -190,4 +200,30 @@ endfunction // _gen_ga
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
\ No newline at end of file
`define WIRE_VME_PINS_CONVENTION(slot_id) \
.VME_AS_n_i(VME_AS_n),\
.VME_SYSRESET_n_i(VME_RST_n),\
.VME_WRITE_n_i(VME_WRITE_n),\
.VME_AM_i(VME_AM),\
.VME_DS_n_i(VME_DS_n),\
.VME_GA_i(_gen_ga_convention(slot_id)),\
.VME_GAP_i(_gen_gap_convention(slot_id)),\
.VME_BERR_o(VME_BERR),\
.VME_DTACK_n_o(VME_DTACK_n),\
.VME_RETRY_n_o(VME_RETRY_n),\
.VME_RETRY_OE_o(VME_RETRY_OE),\
.VME_LWORD_n_b(VME_LWORD_n),\
.VME_ADDR_b(VME_ADDR),\
.VME_DATA_b(VME_DATA),\
.VME_IRQ_o(VME_IRQ_n),\
.VME_IACK_n_i(VME_IACK_n),\
.VME_IACKIN_n_i(VME_IACKIN_n),\
.VME_IACKOUT_n_o(VME_IACKOUT_n),\
.VME_DTACK_OE_o(VME_DTACK_OE),\
.VME_DATA_DIR_o(VME_DATA_DIR),\
.VME_DATA_OE_N_o(VME_DATA_OE_N),\
.VME_ADDR_DIR_o(VME_ADDR_DIR),\
.VME_ADDR_OE_N_o(VME_ADDR_OE_N)
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
Subproject commit 4f414ececa8286f49bc6324425a00b9561884375
Subproject commit 5ffe9f5344e22262d1badeef21b8426d20948368
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
Subproject commit 7911a1387bd47bc74e52957509ba7f303b5880b8
Subproject commit 41415b8141e5466248e55eadd30ba4a68e4b3e21
Subproject commit 633d31749b104d4ca04c569cf3e30c5a6c9902b5
Subproject commit 366ca4dbe1777f5bc98341d2878070a6c6fa350f
Subproject commit c466a66b4d17173d3ee5e18af26a2d263a760aa0
Subproject commit ad01cd0965381808974decabd924c02ce902a3cc
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2013-07-02
-- Last update: 2019-03-21
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -423,21 +423,10 @@ begin -- behave
-- Input: tdc_start_i
-- Output: tdc_start_d
--
-- A synchronizer chain for detecting the relation between clk_tdc_i
-- and clk_ref_i. Since both clocks are almost in phase, the first stage
-- reacts to the falling edge of the reference clock to satisfy setup/hold
-- requirements.
--
p_sync_tdclk_fedge : process(clk_ref_i)
begin
if falling_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
end if;
end process;
p_sync_tdclk_redge : process(clk_ref_i)
begin
if rising_edge(clk_ref_i) then
tdc_start_d(0) <= tdc_start_i;
tdc_start_d(1) <= tdc_start_d(0);
tdc_start_d(2) <= tdc_start_d(1);
end if;
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : fd_channel_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fd_channel_wishbone_slave.wb
-- Created : Wed Dec 4 17:20:17 2013
-- Created : Wed Mar 20 23:27:12 2019
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fd_channel_wishbone_slave.wb
......@@ -22,93 +22,119 @@ package fd_channel_wbgen2_pkg is
type t_fd_channel_in_registers is record
dcr_pg_trig_i : std_logic;
dcr_upd_done_i : std_logic;
end record;
end record;
constant c_fd_channel_in_registers_init_value: t_fd_channel_in_registers := (
dcr_pg_trig_i => '0',
dcr_upd_done_i => '0'
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
);
-- Output registers (WB slave -> user design)
type t_fd_channel_out_registers is record
dcr_enable_o : std_logic;
dcr_mode_o : std_logic;
dcr_pg_arm_o : std_logic;
dcr_update_o : std_logic;
dcr_force_dly_o : std_logic;
dcr_no_fine_o : std_logic;
dcr_force_hi_o : std_logic;
frr_o : std_logic_vector(9 downto 0);
u_starth_o : std_logic_vector(7 downto 0);
u_startl_o : std_logic_vector(31 downto 0);
c_start_o : std_logic_vector(27 downto 0);
f_start_o : std_logic_vector(11 downto 0);
u_endh_o : std_logic_vector(7 downto 0);
u_endl_o : std_logic_vector(31 downto 0);
c_end_o : std_logic_vector(27 downto 0);
f_end_o : std_logic_vector(11 downto 0);
u_delta_o : std_logic_vector(3 downto 0);
c_delta_o : std_logic_vector(27 downto 0);
f_delta_o : std_logic_vector(11 downto 0);
rcr_rep_cnt_o : std_logic_vector(15 downto 0);
rcr_cont_o : std_logic;
end record;
constant c_fd_channel_out_registers_init_value: t_fd_channel_out_registers := (
dcr_enable_o => '0',
dcr_mode_o => '0',
dcr_pg_arm_o => '0',
dcr_update_o => '0',
dcr_force_dly_o => '0',
dcr_no_fine_o => '0',
dcr_force_hi_o => '0',
frr_o => (others => '0'),
u_starth_o => (others => '0'),
u_startl_o => (others => '0'),
c_start_o => (others => '0'),
f_start_o => (others => '0'),
u_endh_o => (others => '0'),
u_endl_o => (others => '0'),
c_end_o => (others => '0'),
f_end_o => (others => '0'),
u_delta_o => (others => '0'),
c_delta_o => (others => '0'),
f_delta_o => (others => '0'),
rcr_rep_cnt_o => (others => '0'),
rcr_cont_o => '0'
);
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component fd_channel_wb_slave is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
clk_ref_i : in std_logic;
regs_i : in t_fd_channel_in_registers;
regs_o : out t_fd_channel_out_registers
);
end component;
end package;
package body fd_channel_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fd_channel_in_registers) return t_fd_channel_in_registers is
variable tmp: t_fd_channel_in_registers;
variable tmp: t_fd_channel_in_registers;
begin
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
tmp.dcr_pg_trig_i := f_x_to_zero(left.dcr_pg_trig_i) or f_x_to_zero(right.dcr_pg_trig_i);
tmp.dcr_upd_done_i := f_x_to_zero(left.dcr_upd_done_i) or f_x_to_zero(right.dcr_upd_done_i);
return tmp;
end function;
end package body;
This diff is collapsed.
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-07-18
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......
This diff is collapsed.
This diff is collapsed.
......@@ -404,7 +404,17 @@ peripheral {
prefix = "ALUTRIG";
type = MONOSTABLE;
};
};
field {
clock = "clk_ref_i";
name = "IDELAY CE (pulse)";
description = "Write 1 to pulse the IDELAY CE line for 1 clock tick.";
prefix = "IDELAY_CE";
type = MONOSTABLE;
};
};
reg {
prefix = "CALR";
......@@ -1031,7 +1041,37 @@ peripheral {
};
};
reg {
name = "FMC Slot ID Register";
description = "Index of the hardware FMC slot the card is in.";
prefix = "FMC_SLOT_ID";
field {
name = "Slot ID";
prefix = "SLOT_ID";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "I/O Delay Adjust Register";
description = "Setup time adjust for certain signals (e.g. TDC_START).";
prefix = "IODELAY_ADJ";
field {
name = "Number of delay line taps.";
prefix = "N_TAPS";
type = SLV;
size = 6;
access_bus = READ_WRITE;
access_dev = READ_WRITE;
load = LOAD_EXT;
};
};
irq {
name = "Timestamp Buffer interrupt.";
description = "Triggers when there are timestamps in the readout buffer";
......
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2011-08-24
-- Last update: 2018-08-03
-- Last update: 2014-03-24
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -65,7 +65,11 @@ entity fine_delay_core is
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_with_debug_output : boolean := false
g_with_debug_output : boolean := false;
-- index of the slot the core is assigned to, written to
-- FMC_SLOT_ID register
g_fmc_slot_id : integer := 0
);
port (
......@@ -195,7 +199,7 @@ entity fine_delay_core is
owr_i : in std_logic;
---------------------------------------------------------------------------
-- Misc signals: I2C EEPROM, FMC presence
-- Misc signals: I2C EEPROM, FMC presence, I/O calibration
---------------------------------------------------------------------------
i2c_scl_o : out std_logic;
......@@ -207,6 +211,11 @@ entity fine_delay_core is
fmc_present_n_i : in std_logic;
idelay_inc_o : out std_logic;
idelay_cal_o : out std_logic;
idelay_ce_o : out std_logic;
idelay_rst_o : out std_logic;
---------------------------------------------------------------------------
-- Wishbone slave (classic/pipelined)
......@@ -358,6 +367,12 @@ architecture rtl of fine_delay_core is
signal dmtd_tag_stb, dbg_tag_in, dbg_tag_out : std_logic;
signal iodelay_ntaps : std_logic_vector(5 downto 0);
signal iodelay_cnt : unsigned(5 downto 0);
signal iodelay_div : unsigned(4 downto 0);
signal iodelay_tick : std_logic;
signal iodelay_cal_done : std_logic;
begin -- rtl
U_WB_Adapter : wb_slave_adapter
......@@ -504,6 +519,8 @@ begin -- rtl
);
U_Acam_TSU : fd_acam_timestamper
generic map (
g_min_pulse_width => 3,
......@@ -554,12 +571,12 @@ begin -- rtl
U_Sync_TDC_Valid_Out : gc_pulse_synchronizer2
port map (
clk_in_i => clk_ref_0_i,
clk_in_i => clk_ref_0_i,
rst_in_n_i => rst_n_ref,
clk_out_i => clk_sys_i,
clk_out_i => clk_sys_i,
rst_out_n_i => rst_n_sys,
d_p_i => tag_valid,
q_p_o => tdc_valid_o);
d_p_i => tag_valid,
q_p_o => tdc_valid_o);
process(clk_ref_0_i)
begin
......@@ -633,12 +650,12 @@ begin -- rtl
U_Sync_Valid_Pulse : gc_pulse_synchronizer2
port map (
clk_in_i => clk_sys_i,
clk_in_i => clk_sys_i,
rst_in_n_i => rst_n_sys,
clk_out_i => clk_ref_0_i,
clk_out_i => clk_ref_0_i,
rst_out_n_i => rst_n_ref,
d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
d_p_i => outx_valid_i(i),
q_p_o => channels(i).tag.valid);
process(clk_sys_i)
begin
......@@ -780,6 +797,7 @@ begin -- rtl
regs_towb_local.gcr_ddr_locked_i <= pll_status_i;
regs_towb_local.gcr_fmc_present_i <= not fmc_present_n_i;
regs_towb_local.fmc_slot_id_slot_id_i <= std_logic_vector(to_unsigned(g_fmc_slot_id, 4 ));
-- Debug PWM driver for adjusting Peltier temperature. Drivers SPI MOSI line
-- with PWM waveform when none of the SPI peripherals is in use (we have no
......@@ -839,5 +857,62 @@ begin -- rtl
gen_without_dbg_out : if(not g_with_debug_output) generate
dbg_o <= (others => '0');
end generate gen_without_dbg_out;
p_handle_iodelay: process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if rst_n_sys = '0' then
idelay_cal_o <= '0';
idelay_inc_o <= '1';
idelay_rst_o <= '0';
idelay_ce_o <= '0';
iodelay_cal_done <= '0';
iodelay_cnt <= (others => '0');
iodelay_div <= (others => '0');
iodelay_tick <= '0';
else
if iodelay_cal_done = '0' then
idelay_cal_o <= '1';
iodelay_cnt <= iodelay_cnt + 1;
if iodelay_cnt = 15 then
iodelay_cnt <= (others => '0');
iodelay_cal_done <= '1';
end if;
else
idelay_cal_o <= '0';
end if;
iodelay_div <= iodelay_div + 1;
if iodelay_div = 0 then
iodelay_tick <= '1';
else
iodelay_tick <= '0';
end if;
if regs_fromwb.iodelay_adj_n_taps_load_o = '1' then
iodelay_cnt <= unsigned(regs_fromwb.iodelay_adj_n_taps_o);
idelay_rst_o <= '1';
iodelay_ntaps <= regs_fromwb.iodelay_adj_n_taps_o;
else
idelay_rst_o <= '0';
end if;
if iodelay_cal_done = '1' and iodelay_tick = '1' and iodelay_cnt /= 0 then
idelay_ce_o <= '1';
iodelay_cnt <= iodelay_cnt - 1;
else
idelay_ce_o <= '0';
end if;
end if;
end if;
end process;
regs_towb_local.iodelay_adj_n_taps_i <= iodelay_ntaps;