hdl: rename s[pv]ec_top to s[pv]ec_fine_delay_top for the clarity of build info data

04f41501 · Tomasz Wlostowski · 41d6ec31 · 04f41501 · 04f41501 · 04f41501
Commit 04f41501 authored Oct 22, 2019 by Tomasz Wlostowski
8 changed files
--- a/hdl/syn/spec/Manifest.py
+++ b/hdl/syn/spec/Manifest.py
@@ -11,7 +11,7 @@ syn_grade = "-3"
 syn_package = "fgg484"
 syn_project = "spec_fine_delay.xise"
 syn_tool = "ise"
-syn_top = "spec_top"
+syn_top = "spec_fine_delay_top"

 spec_template_ucf = ['wr', 'onewire', 'spi']
 board = "spec"

--- a/hdl/top/spec/Manifest.py
+++ b/hdl/top/spec/Manifest.py
-files = ["spec_top.vhd", "spec_top.ucf"]
+files = ["spec_fine_delay_top.vhd", "spec_fine_delay_top.ucf"]

 fetchto = "../../ip_cores"

@@ -10,7 +10,6 @@ modules = {
 	"../../ip_cores/wr-cores",
 	"../../ip_cores/wr-cores/board/spec",
 	"../../ip_cores/gn4124-core",
-	"../../ip_cores/spec",
-	"../../ip_cores/ddr3-sp6-core"
+	"../../ip_cores/spec"
     ]
    }
--- a/hdl/top/spec/spec_top.ucf
+++ b/hdl/top/spec/spec_top.ucf
--- a/hdl/top/spec/spec_top.vhd
+++ b/hdl/top/spec/spec_top.vhd
@@ -374,6 +374,7 @@ begin  -- architecture arch
      sfp_tx_fault_i      => sfp_tx_fault_i,
      sfp_tx_disable_o    => sfp_tx_disable_o,
      sfp_los_i           => sfp_los_i,
+      clk_dmtd_125m_o     => clk_dmtd_125m,
      clk_sys_62m5_o      => clk_sys_62m5,
      rst_sys_62m5_n_o    => rst_sys_62m5_n,
      clk_ref_125m_o      => clk_ref_125m,

--- a/hdl/top/svec/Manifest.py
+++ b/hdl/top/svec/Manifest.py
-files = ["svec_top.vhd", "svec_top.ucf"]
+files = ["svec_fine_delay_top.vhd", "svec_fine_delay_top.ucf"]

 fetchto = "../../ip_cores"

@@ -11,6 +11,5 @@ modules = {
 	"../../ip_cores/wr-cores/board/svec",
 	"../../ip_cores/vme64x-core",
 	"../../ip_cores/svec",
-	"../../ip_cores/ddr3-sp6-core"
     ]
    }
--- a/hdl/top/svec/svec_top.vhd
+++ b/hdl/top/svec/svec_top.vhd
--- a/hdl/top/svec/svec_top.ucf
+++ b/hdl/top/svec/svec_top.ucf
--- a/hdl/top/svec/synthesis_descriptor.vhd
+++ b/hdl/top/svec/synthesis_descriptor.vhd
-------------------------------------------------------------------------------
-- Title      : Fine Delay FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project    : Fine Delay FMC (fmc-delay-1ns-4cha)
-------------------------------------------------------------------------------
-- File       : synthesis_descriptor.vhd
-- Author     : Tomasz Wlostowski
-- Company    : CERN
-- Created    : 2013-04-16
-- Last update: 2014-03-18
-- Platform   : FPGA-generic
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SVEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-library ieee;
-use ieee.STD_LOGIC_1164.all;
-use work.wishbone_pkg.all;
-
-package synthesis_descriptor is
-  
-constant c_sdb_synthesis_info : t_sdb_synthesis :=
-  (
-    syn_module_name => "svec-fine-delay ",              
-    syn_commit_id => "a3f676c402a931c43ed2654bddd7dbaf",
-    syn_tool_name => "ISE     ",
-    syn_tool_version => x"00000147",
-    syn_date => x"20141209",
-    syn_username => "twlostow       ");
-
-constant c_sdb_repo_url : t_sdb_repo_url :=
-  (
-    repo_url => "git://ohwr.org/fmc-projects/fmc-delay-1ns-8cha.git             " 
-  );
-
-end package synthesis_descriptor;