added WR timecode input and aux clock PLL control signals. Changed SPI core to custom module with hw arbitration of the PLL DAC access

fd_delay_channel_driver: fixed possible FSM hang when the card is disabled during generation of a pulse, implemented new calibration scheme

fd_acam_timestamper: now generates calibration start pulses even if BYPASS=1, extended host read timing to avoid SI problems

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@23 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@22 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@21 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@20 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

Sch/PCB: Updated pad stacks to fit PCB manufacturer's minimum IAR requirement. Removed 0-sized apertures from fiducials.

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@19 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@18 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@17 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

Sch/PCB: Added CERN/OHWR notice, updated copyright and stackup info, added script for PDF generation

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@16 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

Sch/PCB: Changed clock connection to the output flip-flops, changed resistors to resistor arrays, added 2 layers to improve signal integrity and differential pair routing, changed footprints and schematic symbols to the CERN ones.

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@15 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@14 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d

git-svn-id: http://svn.ohwr.org/fmc-delay-1ns-8cha@13 1bcb1fca-75bf-43fa-9ae8-4d3013b6ad5d