Commit f7b7c9a0 authored by Tom Levens's avatar Tom Levens

Update FSM

Ensure transition to stop state only happens at end of sequence and that
start only happens when stopped.
parent e502f504
...@@ -70,16 +70,14 @@ architecture syn of Fsm is ...@@ -70,16 +70,14 @@ architecture syn of Fsm is
return to_unsigned(t_State'pos(State), 3); return to_unsigned(t_State'pos(State), 3);
end function; end function;
constant c_ResetState: t_State := s_Stop; signal State: t_State := s_Stop;
signal State: t_State := c_ResetState;
begin begin
pFsmTransitions: process (Clk_ik) is begin pFsmTransitions: process (Clk_ik) is begin
if rising_edge(Clk_ik) then if rising_edge(Clk_ik) then
if Reset_ir = '1' then if Reset_ir = '1' then
State <= c_ResetState; State <= s_Stop;
else else
State <= State; State <= State;
if ModeLoad_i = '1' then if ModeLoad_i = '1' then
...@@ -94,6 +92,10 @@ begin ...@@ -94,6 +92,10 @@ begin
else else
-- separate states -- separate states
case State is case State is
when s_Stop =>
if (ModeLoad_i = '1') and (Mode_i /= e_ModeStop) then
State <= s_WaitForTrigger;
end if;
when s_WaitForTrigger => when s_WaitForTrigger =>
if Trigger_i = '1' then if Trigger_i = '1' then
State <= s_Generating; State <= s_Generating;
...@@ -103,11 +105,11 @@ begin ...@@ -103,11 +105,11 @@ begin
State <= s_Outputting; State <= s_Outputting;
end if; end if;
when s_Outputting => when s_Outputting =>
if (StreamReset_i = '1') and (Mode_i = e_ModeSingle) then if (StreamReset_i = '1') and ((Mode_i = e_ModeSingle) or (Mode_i = e_ModeStop)) then
State <= s_Stop; State <= s_Stop;
end if; end if;
when others => when others =>
State <= c_ResetState; State <= s_Stop;
end case; end case;
end if; end if;
end if; end if;
......
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