removed one clock domain in top-level, now everything runs on 62.5 MHz; added…

removed one clock domain in top-level, now everything runs on 62.5 MHz; added few default values for simulation

removed one clock domain in top-level, now everything runs on 62.5 MHz; added…
removed one clock domain in top-level, now everything runs on 62.5 MHz; added few default values for simulation
e938e57a · Jan Pospisil · 0d512ced · e938e57a · e938e57a · e938e57a
Commit e938e57a authored Aug 18, 2016 by Jan Pospisil
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Showing with 55 additions and 122 deletions

SvecTopFfpg.vhd hdl/svec/rtl/SvecTopFfpg.vhd +22 -63

make hdl/svec/sim/testbench/make +0 -6

SvecFfpg.xise hdl/svec/syn/SvecFfpg.xise +33 -53

No files found.
--- a/hdl/svec/rtl/SvecTopFfpg.vhd
+++ b/hdl/svec/rtl/SvecTopFfpg.vhd
@@ -15,7 +15,7 @@ entity SvecTopFfpg is
        -- Local 20MHz VCXO oscillator
        Clk20_ik: in std_logic;
-        -- Reset from system fpga
+        -- Reset from system FPGA
        Reset_inr: in std_logic;
        -- DAC interface (20MHz and 25MHz VCXO)
@@ -31,7 +31,7 @@ entity SvecTopFfpg is
        FpLedsLine_ob2: out std_logic_vector(1 downto 0);
        FpLedsColumn_ob4: out std_logic_vector(3 downto 0);
-        -- Carrier I2C eeprom
+        -- Carrier I2C EEPROM
        CarrierScl_io: inout std_logic;
        CarrierSda_io: inout std_logic;
@@ -206,8 +206,7 @@ architecture rtl of SvecTopFfpg is
        RefJitter => 0.016
    );
-    constant c_ClkSysFrequency: positive := 125_000_000; -- in Hz
+    constant c_ClkSysFrequency: positive :=  62_500_000; -- in Hz
-    constant c_ClkVmeFrequency: positive :=  62_500_000; -- in Hz
    -- SVEC carrier CSR constants
    constant c_CarrierType: std_logic_vector(15 downto 0) := X"0002";
@@ -265,14 +264,15 @@ architecture rtl of SvecTopFfpg is
    signal Clk20Buffered_k: std_logic;
    signal PllLocked, PllFeedback: std_logic;
    signal ClkSysUnbuffered_k, ClkSys_k: std_logic;
-    signal ClkVmeUnbuffered_k, ClkVme_k: std_logic;
    signal PowerupResetCounter: unsigned(7 downto 0) := (others => '0');
-    signal ResetVme_r, ResetVme_nr: std_logic;
+    signal ResetSys_r: std_logic := '1';
-    signal ResetSys_r, ResetSys_nr: std_logic;
+    signal ResetSys_nr: std_logic;
-    signal SwResetFmc0_r, SwResetFmc0Out_n, SwResetFmc0In_n, SwResetFmc0Load: std_logic;
+    signal SwResetFmc0_r: std_logic := '0';
+    signal SwResetFmc0Out_n, SwResetFmc0In_n, SwResetFmc0Load: std_logic;
    signal Fmc0Reset_r: std_logic;
-    signal SwResetFmc1_r, SwResetFmc1Out_n, SwResetFmc1In_n, SwResetFmc1Load: std_logic;
+    signal SwResetFmc1_r: std_logic := '0';
+    signal SwResetFmc1Out_n, SwResetFmc1In_n, SwResetFmc1Load: std_logic;
    signal Fmc1Reset_r: std_logic;
    signal VmeAddr_b_out: std_logic_vector(31 downto 1);
@@ -280,8 +280,6 @@ architecture rtl of SvecTopFfpg is
    signal VmeData_b_out: std_logic_vector(31 downto 0);
    signal VmeData_dir_int: std_logic;
    signal VmeLword_n_b_out: std_logic;
-    signal VmeMaster_in, VmeSync_master_in: t_wishbone_master_in;
-    signal VmeMaster_out, VmeSync_master_out: t_wishbone_master_out;
    -- Wishbone buse(s) from crossbar master port(s)
    signal CnxMasterOut: t_wishbone_master_out_array(c_NumWbSlaves-1 downto 0);
@@ -343,16 +341,13 @@ begin
            CLKOUT0_DIVIDE => f_ComputePllDivider(c_PllSettings, c_ClkSysFrequency),
            CLKOUT0_PHASE => 0.000,
            CLKOUT0_DUTY_CYCLE => 0.500,
-            CLKOUT1_DIVIDE => f_ComputePllDivider(c_PllSettings, c_ClkVmeFrequency),
-            CLKOUT1_PHASE => 0.000,
-            CLKOUT1_DUTY_CYCLE => 0.500,
            CLKIN_PERIOD => (1.0)/real(c_PllSettings.InputFrequency)*1.0e9, -- in ns
            REF_JITTER => c_PllSettings.RefJitter
        )
        port map (
            CLKFBOUT => PllFeedback,
            CLKOUT0 => ClkSysUnbuffered_k,
-            CLKOUT1 => ClkVmeUnbuffered_k,
+            CLKOUT1 => open,
            CLKOUT2 => open,
            CLKOUT3 => open,
            CLKOUT4 => open,
@@ -363,12 +358,6 @@ begin
            CLKIN => Clk20Buffered_k
        );
-    cClkVmeBuf: BUFG
-        port map (
-            I => ClkVmeUnbuffered_k,
-            O => ClkVme_k
-        );
    cClkSysBuf: BUFG
        port map (
            I => ClkSysUnbuffered_k,
@@ -379,44 +368,35 @@ begin
    -- System reset
    ------------------------------------------------------------------------------
-    pPowerupReset: process (ClkVme_k) begin
+    pPowerupReset: process (ClkSys_k) begin
-        if rising_edge(ClkVme_k) then
+        if rising_edge(ClkSys_k) then
            if (VmeSysreset_n_i = '0' or Reset_inr = '0') then
-                ResetVme_nr <= '0';
+                ResetSys_r <= '1';
            elsif PllLocked = '1' then
                if PowerupResetCounter = "11111111" then
-                    ResetVme_nr <= '1';
+                    ResetSys_r <= '0';
                else
-                    ResetVme_nr <= '0';
+                    ResetSys_r <= '1';
                    PowerupResetCounter <= PowerupResetCounter + 1;
                end if;
            else
-                ResetVme_nr <= '0';
+                ResetSys_r <= '1';
                PowerupResetCounter <= (others => '0');
            end if;
        end if;
    end process;
-    ResetVme_r <= not ResetVme_nr;
-    --System reset synchronisation to system clock domain
-    cResetSyncerSys: entity work.ResetSyncer(syn)
-        port map (
-            Clk_ik => ClkSys_k,
-            Reset_ira => ResetVme_r,
-            Reset_or => ResetSys_r
-        );
    ResetSys_nr <= not ResetSys_r;
    ------------------------------------------------------------------------------
    -- VME interface
    ------------------------------------------------------------------------------
    cVmeCore: entity work.xvme64x_core(wrapper)
        port map (
-            clk_i => ClkVme_k,
+            clk_i => ClkSys_k,
-            rst_n_i => ResetVme_nr,
+            rst_n_i => ResetSys_nr,
            VME_AS_n_i => VmeAs_n_i,
-            VME_RST_n_i => ResetVme_nr,
+            VME_RST_n_i => VmeSysreset_n_i,
            VME_WRITE_n_i => VmeWrite_n_i,
            VME_AM_i => VmeAm_i,
            VME_DS_n_i => VmeDs_n_i,
@@ -440,8 +420,8 @@ begin
            VME_DATA_OE_N_o => VmeData_oe_n_o,
            VME_ADDR_DIR_o => VmeAddr_dir_int,
            VME_ADDR_OE_N_o => VmeAddr_oe_n_o,
-            master_o => VmeMaster_out,
+            master_o => CnxSlaveIn(c_MasterVmeId),
-            master_i => VmeMaster_in,
+            master_i => CnxSlaveOut(c_MasterVmeId),
            irq_i => '0'
        );
@@ -459,27 +439,6 @@ begin
    VmeAddr_dir_o <= VmeAddr_dir_int;
    VmeData_dir_o <= VmeData_dir_int;
-    -- Wishbone bus synchronisation from VME clock to system clock
-    cWbClockCrossing: entity work.xwb_clock_crossing
-        generic map (
-            g_size => 16
-        )
-        port map (
-            slave_clk_i => ClkVme_k,
-            slave_rst_n_i => ResetVme_nr,
-            slave_i => VmeMaster_out,
-            slave_o => VmeMaster_in,
-            master_clk_i => ClkSys_k,
-            master_rst_n_i => ResetSys_nr,
-            master_i => VmeSync_master_in,
-            master_o => VmeSync_master_out,
-            slave_ready_o => open,
-            slave_stall_i => '0'
-        );
-    CnxSlaveIn(c_MasterVmeId) <= VmeSync_master_out;
-    VmeSync_master_in <= CnxSlaveOut(c_MasterVmeId);
    ------------------------------------------------------------------------------
    -- CSR wishbone crossbar
    ------------------------------------------------------------------------------

--- a/hdl/svec/sim/testbench/make
+++ b/hdl/svec/sim/testbench/make
@@ -80,12 +80,6 @@ vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme6
 vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
 vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
-vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
-vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
-vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd
-vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
-vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
 vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
 vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
 vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd

--- a/hdl/svec/syn/SvecFfpg.xise
+++ b/hdl/svec/syn/SvecFfpg.xise