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FMC DEL 1ns 2cha
Commit e938e57a authored by Jan Pospisil's avatar Jan Pospisil
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removed one clock domain in top-level, now everything runs on 62.5 MHz; added… 

removed one clock domain in top-level, now everything runs on 62.5 MHz; added few default values for simulation
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Showing with 55 additions and 122 deletions
hdl/svec/rtl/SvecTopFfpg.vhd
View file @ e938e57a
......@@ -15,7 +15,7 @@ entity SvecTopFfpg is
-- Local 20MHz VCXO oscillator
Clk20_ik: in std_logic;
-- Reset from system fpga
-- Reset from system FPGA
Reset_inr: in std_logic;
-- DAC interface (20MHz and 25MHz VCXO)
......@@ -31,7 +31,7 @@ entity SvecTopFfpg is
FpLedsLine_ob2: out std_logic_vector(1 downto 0);
FpLedsColumn_ob4: out std_logic_vector(3 downto 0);
-- Carrier I2C eeprom
-- Carrier I2C EEPROM
CarrierScl_io: inout std_logic;
CarrierSda_io: inout std_logic;
......@@ -206,8 +206,7 @@ architecture rtl of SvecTopFfpg is
RefJitter => 0.016
);
constant c_ClkSysFrequency: positive := 125_000_000; -- in Hz
constant c_ClkVmeFrequency: positive := 62_500_000; -- in Hz
constant c_ClkSysFrequency: positive := 62_500_000; -- in Hz
-- SVEC carrier CSR constants
constant c_CarrierType: std_logic_vector(15 downto 0) := X"0002";
......@@ -265,14 +264,15 @@ architecture rtl of SvecTopFfpg is
signal Clk20Buffered_k: std_logic;
signal PllLocked, PllFeedback: std_logic;
signal ClkSysUnbuffered_k, ClkSys_k: std_logic;
signal ClkVmeUnbuffered_k, ClkVme_k: std_logic;
signal PowerupResetCounter: unsigned(7 downto 0) := (others => '0');
signal ResetVme_r, ResetVme_nr: std_logic;
signal ResetSys_r, ResetSys_nr: std_logic;
signal SwResetFmc0_r, SwResetFmc0Out_n, SwResetFmc0In_n, SwResetFmc0Load: std_logic;
signal ResetSys_r: std_logic := '1';
signal ResetSys_nr: std_logic;
signal SwResetFmc0_r: std_logic := '0';
signal SwResetFmc0Out_n, SwResetFmc0In_n, SwResetFmc0Load: std_logic;
signal Fmc0Reset_r: std_logic;
signal SwResetFmc1_r, SwResetFmc1Out_n, SwResetFmc1In_n, SwResetFmc1Load: std_logic;
signal SwResetFmc1_r: std_logic := '0';
signal SwResetFmc1Out_n, SwResetFmc1In_n, SwResetFmc1Load: std_logic;
signal Fmc1Reset_r: std_logic;
signal VmeAddr_b_out: std_logic_vector(31 downto 1);
......@@ -280,8 +280,6 @@ architecture rtl of SvecTopFfpg is
signal VmeData_b_out: std_logic_vector(31 downto 0);
signal VmeData_dir_int: std_logic;
signal VmeLword_n_b_out: std_logic;
signal VmeMaster_in, VmeSync_master_in: t_wishbone_master_in;
signal VmeMaster_out, VmeSync_master_out: t_wishbone_master_out;
-- Wishbone buse(s) from crossbar master port(s)
signal CnxMasterOut: t_wishbone_master_out_array(c_NumWbSlaves-1 downto 0);
......@@ -343,16 +341,13 @@ begin
CLKOUT0_DIVIDE => f_ComputePllDivider(c_PllSettings, c_ClkSysFrequency),
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => f_ComputePllDivider(c_PllSettings, c_ClkVmeFrequency),
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => (1.0)/real(c_PllSettings.InputFrequency)*1.0e9, -- in ns
REF_JITTER => c_PllSettings.RefJitter
)
port map (
CLKFBOUT => PllFeedback,
CLKOUT0 => ClkSysUnbuffered_k,
CLKOUT1 => ClkVmeUnbuffered_k,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
......@@ -363,12 +358,6 @@ begin
CLKIN => Clk20Buffered_k
);
cClkVmeBuf: BUFG
port map (
I => ClkVmeUnbuffered_k,
O => ClkVme_k
);
cClkSysBuf: BUFG
port map (
I => ClkSysUnbuffered_k,
......@@ -379,44 +368,35 @@ begin
-- System reset
------------------------------------------------------------------------------
pPowerupReset: process (ClkVme_k) begin
if rising_edge(ClkVme_k) then
pPowerupReset: process (ClkSys_k) begin
if rising_edge(ClkSys_k) then
if (VmeSysreset_n_i = '0' or Reset_inr = '0') then
ResetVme_nr <= '0';
ResetSys_r <= '1';
elsif PllLocked = '1' then
if PowerupResetCounter = "11111111" then
ResetVme_nr <= '1';
ResetSys_r <= '0';
else
ResetVme_nr <= '0';
ResetSys_r <= '1';
PowerupResetCounter <= PowerupResetCounter + 1;
end if;
else
ResetVme_nr <= '0';
ResetSys_r <= '1';
PowerupResetCounter <= (others => '0');
end if;
end if;
end process;
ResetVme_r <= not ResetVme_nr;
--System reset synchronisation to system clock domain
cResetSyncerSys: entity work.ResetSyncer(syn)
port map (
Clk_ik => ClkSys_k,
Reset_ira => ResetVme_r,
Reset_or => ResetSys_r
);
ResetSys_nr <= not ResetSys_r;
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
cVmeCore: entity work.xvme64x_core(wrapper)
port map (
clk_i => ClkVme_k,
rst_n_i => ResetVme_nr,
clk_i => ClkSys_k,
rst_n_i => ResetSys_nr,
VME_AS_n_i => VmeAs_n_i,
VME_RST_n_i => ResetVme_nr,
VME_RST_n_i => VmeSysreset_n_i,
VME_WRITE_n_i => VmeWrite_n_i,
VME_AM_i => VmeAm_i,
VME_DS_n_i => VmeDs_n_i,
......@@ -440,8 +420,8 @@ begin
VME_DATA_OE_N_o => VmeData_oe_n_o,
VME_ADDR_DIR_o => VmeAddr_dir_int,
VME_ADDR_OE_N_o => VmeAddr_oe_n_o,
master_o => VmeMaster_out,
master_i => VmeMaster_in,
master_o => CnxSlaveIn(c_MasterVmeId),
master_i => CnxSlaveOut(c_MasterVmeId),
irq_i => '0'
);
......@@ -459,27 +439,6 @@ begin
VmeAddr_dir_o <= VmeAddr_dir_int;
VmeData_dir_o <= VmeData_dir_int;
-- Wishbone bus synchronisation from VME clock to system clock
cWbClockCrossing: entity work.xwb_clock_crossing
generic map (
g_size => 16
)
port map (
slave_clk_i => ClkVme_k,
slave_rst_n_i => ResetVme_nr,
slave_i => VmeMaster_out,
slave_o => VmeMaster_in,
master_clk_i => ClkSys_k,
master_rst_n_i => ResetSys_nr,
master_i => VmeSync_master_in,
master_o => VmeSync_master_out,
slave_ready_o => open,
slave_stall_i => '0'
);
CnxSlaveIn(c_MasterVmeId) <= VmeSync_master_out;
VmeSync_master_in <= CnxSlaveOut(c_MasterVmeId);
------------------------------------------------------------------------------
-- CSR wishbone crossbar
------------------------------------------------------------------------------
......
hdl/svec/sim/testbench/make
View file @ e938e57a
......@@ -80,12 +80,6 @@ vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme6
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_sync_register.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd
vcom -2008 -reportprogress 300 -work work ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd
......
hdl/svec/syn/SvecFfpg.xise
View file @ e938e57a
......@@ -380,31 +380,31 @@
<files>
<file xil_pn:name="../rtl/SvecTopFfpg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file>
<file xil_pn:name="../../ffpg/rtl/FfpgCore.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file>
<file xil_pn:name="../../ffpg/rtl/FfpgSlave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DacsController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file>
<file xil_pn:name="../../ffpg/rtl/WbSlaveWrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGenerator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/Fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
......@@ -420,7 +420,7 @@
</file>
<file xil_pn:name="../../ffpg/rtl/RegSyncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../../ffpg/rtl/ShiftRegister.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
......@@ -428,7 +428,7 @@
</file>
<file xil_pn:name="../../ffpg/rtl/ResetSyncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ffpg/rtl/EdgeDetector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
......@@ -440,7 +440,7 @@
</file>
<file xil_pn:name="../../ffpg/rtl/PulseGeneratorTime.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../../ffpg/rtl/PulseGenerator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
......@@ -448,7 +448,7 @@
</file>
<file xil_pn:name="../../ffpg/rtl/ffpg_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../../ip_cores/wishbone-gen/lib/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
......@@ -468,7 +468,7 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
......@@ -476,11 +476,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
......@@ -488,11 +488,11 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
......@@ -508,15 +508,15 @@
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
......@@ -548,23 +548,23 @@
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/xvme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../../ip_cores/vme64x-core/hdl/vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
......@@ -610,37 +610,17 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/genrams/generic/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_register.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
......@@ -652,30 +632,30 @@
</file>
<file xil_pn:name="../rtl/carrier_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="86"/>
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file>
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<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
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<file xil_pn:name="../../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
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<file xil_pn:name="../rtl/HeartBeat.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
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<file xil_pn:name="../../ffpg/rtl/DelayedPulseGenerator/DelayedPulseGeneratorsCdc.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
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<file xil_pn:name="../../ffpg/rtl/Ad9512Syncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file>
</files>
......
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