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FMC DEL 1ns 2cha
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FMC DEL 1ns 2cha
Commits
b88e6aa7
Commit
b88e6aa7
authored
Dec 19, 2016
by
Jan Pospisil
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white-spaces clean-up
parent
b21ab4a0
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ChangeDetector.vhd
hdl/ffpg/rtl/ChangeDetector.vhd
+16
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hdl/ffpg/rtl/ChangeDetector.vhd
View file @
b88e6aa7
...
@@ -2,25 +2,25 @@ library ieee;
...
@@ -2,25 +2,25 @@ library ieee;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
std_logic_1164
.
all
;
entity
ChangeDetector
is
entity
ChangeDetector
is
port
(
port
(
Clk_ik
:
in
std_logic
;
Clk_ik
:
in
std_logic
;
Signal_ib
:
in
std_logic_vector
;
Signal_ib
:
in
std_logic_vector
;
Change_o
:
out
std_logic
Change_o
:
out
std_logic
);
);
end
entity
;
end
entity
;
architecture
syn
of
ChangeDetector
is
architecture
syn
of
ChangeDetector
is
signal
History_b
:
std_logic_vector
(
Signal_ib
'range
)
:
=
(
others
=>
'0'
);
signal
History_b
:
std_logic_vector
(
Signal_ib
'range
)
:
=
(
others
=>
'0'
);
begin
begin
pDelay
:
process
(
Clk_ik
)
is
begin
pDelay
:
process
(
Clk_ik
)
is
begin
if
rising_edge
(
Clk_ik
)
then
if
rising_edge
(
Clk_ik
)
then
History_b
<=
Signal_ib
;
History_b
<=
Signal_ib
;
end
if
;
end
if
;
end
process
;
end
process
;
pDetection
:
process
(
Signal_ib
,
History_b
)
is
pDetection
:
process
(
Signal_ib
,
History_b
)
is
variable
Result
:
std_logic
;
variable
Result
:
std_logic
;
begin
begin
...
@@ -30,5 +30,5 @@ begin
...
@@ -30,5 +30,5 @@ begin
end
loop
;
end
loop
;
Change_o
<=
Result
;
Change_o
<=
Result
;
end
process
;
end
process
;
end
architecture
;
end
architecture
;
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