white-spaces clean-up

b88e6aa7 · Jan Pospisil · b21ab4a0 · b88e6aa7
Commit b88e6aa7 authored Dec 19, 2016 by Jan Pospisil
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Showing with 16 additions and 16 deletions

ChangeDetector.vhd hdl/ffpg/rtl/ChangeDetector.vhd +16 -16

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--- a/hdl/ffpg/rtl/ChangeDetector.vhd
+++ b/hdl/ffpg/rtl/ChangeDetector.vhd
@@ -2,25 +2,25 @@ library ieee;
 use ieee.std_logic_1164.all;

 entity ChangeDetector is
-	port (
-		Clk_ik: in std_logic;
-		Signal_ib: in std_logic_vector;
-		Change_o: out std_logic
-	);
+    port (
+        Clk_ik: in std_logic;
+        Signal_ib: in std_logic_vector;
+        Change_o: out std_logic
+    );
 end entity;

 architecture syn of ChangeDetector is
-	
-	signal History_b: std_logic_vector(Signal_ib'range) := (others => '0');
-	
+    
+    signal History_b: std_logic_vector(Signal_ib'range) := (others => '0');
+    
 begin
-	
-	pDelay: process (Clk_ik) is begin
-		if rising_edge(Clk_ik) then
-			History_b <= Signal_ib;
-		end if;
-	end process;
-	
+    
+    pDelay: process (Clk_ik) is begin
+        if rising_edge(Clk_ik) then
+            History_b <= Signal_ib;
+        end if;
+    end process;
+    
    pDetection: process (Signal_ib, History_b) is
        variable Result: std_logic;
    begin
@@ -30,5 +30,5 @@ begin
        end loop;
        Change_o <= Result;
    end process;
-	
+    
 end architecture;