Commit b21ab4a0 authored by Jan Pospisil's avatar Jan Pospisil

added wbgen2 generated files

parent 521618bf
/doc/manual/ffpg_csr.tex
/doc/manual/svec/carrier_csr.tex
/hdl/*/wb_gen/*.h
/hdl/*/sim/testbench/work/*
/hdl/*/sim/testbench/tr_db.log
/hdl/*/sim/testbench/transcript
......@@ -8,10 +5,4 @@
/hdl/*/sim/testbench/vsim.wlf
/hdl/*/sim/testbench/wlf*
/hdl/*/sim/testbench/*.vstf
/hdl/ffpg/rtl/ffpg_csr.vhd
/hdl/ffpg/rtl/ffpg_csr_pkg.vhd
/hdl/ffpg/sim/testbench/ffpg_csr.svh
/hdl/svec/syn
/hdl/svec/rtl/carrier_csr.vhd
/hdl/svec/sim/testbench/carrier_csr.svh
......@@ -3,27 +3,26 @@
<TITLE>ffpg_csr</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
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.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
<!--
BODY { background: white; color: black; font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
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.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
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.td_desc { padding: 3px; }
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.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
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th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
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</STYLE>
</HEAD>
<BODY>
......@@ -2579,38 +2578,47 @@ CLOCK_INFRASTRUCTURE_BUSY
</table>
<ul>
<li><b>
[0]
CLOCK_INFRASTRUCTURE_BUSY
</b>[<i>read-only</i>]: Clock infrastructure configuration in progress
<br>Status of the clock infrastructure configuration<br>0: configuration done<br>1: configuration in progress
<li><b>
[1]
DAC_VCXO_BUSY
</b>[<i>read-only</i>]: VCXO DAC busy
<br>Status of the VCXO DAC communication<br>0: DAC idle, value already set<br>1: DAC busy, communication in progress
<li><b>
[2]
DAC_TRIGGER_BUSY
</b>[<i>read-only</i>]: Trigger DAC busy
<br>Status of the trigger DAC communication<br>0: DAC idle, value already set<br>1: DAC busy, communication in progress
<li><b>
[3]
DELAY_CONFIGURATION_BUSY
</b>[<i>read-only</i>]: Delay configuration in progress
<br>Status of the delay configuration<br>0: configuration done<br>1: configuration in progress
<li><b>
[4]
CHANNEL_1_OE
</b>[<i>read-only</i>]: Channel 1 output enabled
<br>Channel 1 output enabled<br>0: output disabled<br>1: output enabled
<li><b>
[5]
CHANNEL_2_OE
</b>[<i>read-only</i>]: Channel 2 output enabled
<br>Channel 2 output enabled<br>0: output disabled<br>1: output enabled
<li><b>
[6]
CHANNEL_1_RUNNING
</b>[<i>read-only</i>]: Pulse generator channel 1 running
<br>Pulse generator channel 1 running<br>0: channel 1 is not running<br>1: channel 1 is running, pulses are generated
<li><b>
[7]
CHANNEL_2_RUNNING
</b>[<i>read-only</i>]: Pulse generator channel 2 running
<br>Pulse generator channel 2 running<br>0: channel 2 is not running<br>1: channel 2 is running, pulses are generated
<li><b>
[8]
INPUT_CLOCK_STABLE
</b>[<i>read-only</i>]: Input clock stable
<br>Indicates the stability of the input clock.<br>0: input clock not present or not stable<br>1: input clock present and stable
......@@ -2869,32 +2877,40 @@ CLOCK_SELECTION[1:0]
</table>
<ul>
<li><b>
[2:0]
CLOCK_SELECTION
</b>[<i>read/write</i>]: Clock source selection
<br>0 (default): external clock used (connector on the front panel)<br>1: FPGA loop clock used<br>2: on-board VCXO clock used
<li><b>
[2]
CH1_OE
</b>[<i>read/write</i>]: CH1 output enable
<li><b>
[3]
CH2_OE
</b>[<i>read/write</i>]: CH2 output enable
<li><b>
[6:4]
CH1_MODE
</b>[<i>read/write</i>]: CH1 mode selection
<br>0 (default): stopped (no output generated)<br>1: continuous (non-stop memory looping)<br>2: one-shot (loop memory just once)
<li><b>
[8:6]
CH2_MODE
</b>[<i>read/write</i>]: CH2 mode selection
<br>0 (default): stopped (no output generated)<br>1: continuous (non-stop memory looping)<br>2: one-shot (loop memory just once)
<li><b>
[8]
LED_TEST
</b>[<i>read/write</i>]: LED test
<br>If set to 1, all LEDs on the FFPG front panel will be blinking.
<li><b>
[9]
AD9512_SYNC
</b>[<i>write-only</i>]: AD9512 Synchronization
<br>When written with 1 AD9512 dividers synchronization is performed. It automatically clear to 0.
<li><b>
[10]
FINE_DELAY_ENABLE
</b>[<i>read/write</i>]: AD9512 OUT4 fine delay enable
<br>If set to 1, fine delay on OUT4 output of AD9512 is enabled. Fine delay itself can be set in a separate register.
......@@ -3156,6 +3172,7 @@ VCXO_VOLTAGE[7:0]
</table>
<ul>
<li><b>
[16:0]
VCXO_VOLTAGE
</b>[<i>read/write</i>]: VCXO voltage register value
</ul>
......@@ -3416,6 +3433,7 @@ CLOCK_RATIO_M1[4:0]
</table>
<ul>
<li><b>
[5:0]
CLOCK_RATIO_M1
</b>[<i>read/write</i>]: Clock ratio-1
</ul>
......@@ -3676,6 +3694,7 @@ CH1_DELAY_SET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH1_DELAY_SET
</b>[<i>read/write</i>]: CH1 SET delay
</ul>
......@@ -3936,6 +3955,7 @@ CH1_DELAY_RESET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH1_DELAY_RESET
</b>[<i>read/write</i>]: CH1 RES delay
</ul>
......@@ -4196,6 +4216,7 @@ CH2_DELAY_SET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH2_DELAY_SET
</b>[<i>read/write</i>]: CH2 SET delay
</ul>
......@@ -4456,6 +4477,7 @@ CH2_DELAY_RESET[7:0]
</table>
<ul>
<li><b>
[10:0]
CH2_DELAY_RESET
</b>[<i>read/write</i>]: CH2 RES delay
</ul>
......@@ -4716,6 +4738,7 @@ TRIGGER_THRESHOLD[7:0]
</table>
<ul>
<li><b>
[16:0]
TRIGGER_THRESHOLD
</b>[<i>read/write</i>]: Trigger threshold voltage register value
</ul>
......@@ -4976,6 +4999,7 @@ OVERFLOW[7:0]
</table>
<ul>
<li><b>
[16:0]
OVERFLOW
</b>[<i>read/write</i>]: Overflow value
</ul>
......@@ -5236,6 +5260,7 @@ CH1_TRIGGER_LATENCY[7:0]
</table>
<ul>
<li><b>
[16:0]
CH1_TRIGGER_LATENCY
</b>[<i>read/write</i>]: Trigger latency value
</ul>
......@@ -5496,6 +5521,7 @@ FREQUENCY[7:0]
</table>
<ul>
<li><b>
[32:0]
FREQUENCY
</b>[<i>read-only</i>]: Clock frequency value
</ul>
......@@ -5756,6 +5782,7 @@ DEBUG[7:0]
</table>
<ul>
<li><b>
[32:0]
DEBUG
</b>[<i>read-only</i>]: Debug field
</ul>
......@@ -6016,12 +6043,15 @@ REVISION[7:0]
</table>
<ul>
<li><b>
[12:0]
REVISION
</b>[<i>read-only</i>]: Revision
<li><b>
[22:12]
MINOR
</b>[<i>read-only</i>]: Minor version
<li><b>
[32:22]
MAJOR
</b>[<i>read-only</i>]: Major version
</ul>
......@@ -6282,6 +6312,7 @@ CH2_TRIGGER_LATENCY[7:0]
</table>
<ul>
<li><b>
[16:0]
CH2_TRIGGER_LATENCY
</b>[<i>read/write</i>]: Trigger latency value
</ul>
......@@ -6542,12 +6573,15 @@ VALUE[4:0]
</table>
<ul>
<li><b>
[5:0]
VALUE
</b>[<i>read/write</i>]: AD9512 OUT4 fine delay value
<li><b>
[8:5]
CURRENT
</b>[<i>read/write</i>]: Ramp current
<li><b>
[11:8]
CAPACITORS
</b>[<i>read/write</i>]: Ramp capacitors
</ul>
......
......@@ -3,27 +3,26 @@
<TITLE>carrier_csr</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
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.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
<!--
BODY { background: white; color: black; font-family: Arial,Helvetica; font-size:12; }
h1 { font-family: Trebuchet MS,Arial,Helvetica; font-size:30; color:#404040; }
h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
h3 { font-family: Trebuchet MS,Arial,Helvetica; font-size:16; color:#404040; }
.td_arrow_left { padding:0px; background: #ffffff; text-align: right; font-size:12;}
.td_arrow_right { padding:0px; background: #ffffff; text-align: left; font-size:12;}
.td_code { font-family:Courier New,Courier; padding: 3px; }
.td_desc { padding: 3px; }
.td_sym_center { background: #e0e0f0; padding: 3px; }
.td_port_name { font-family:Courier New,Courier; background: #e0e0f0; text-align: right; font-weight:bold;padding: 3px; width:200px; }
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.td_pblock_right { font-family:Courier New,Courier; background: #e0e0f0; padding: 0px; text-align: right; }
.td_bit { background: #ffffff; color:#404040; font-size:10; width: 70px; font-family:Courier New,Courier; padding: 3px; text-align:center; }
.td_field { background: #e0e0f0; padding: 3px; text-align:center; }
.td_unused { background: #a0a0a0; padding: 3px; text-align:center; }
th { font-weight:bold; color:#ffffff; background: #202080; padding:3px; }
.tr_even { background: #f0eff0; }
.tr_odd { background: #e0e0f0; }
-->
</STYLE>
</HEAD>
<BODY>
......@@ -760,14 +759,17 @@ PCB_REV[4:0]
</table>
<ul>
<li><b>
[5:0]
PCB_REV
</b>[<i>read-only</i>]: PCB revision
<br>Binary coded PCB layout revision.
<li><b>
[16:5]
RESERVED
</b>[<i>read-only</i>]: Reserved register
<br>Ignore on read, write with 0's.
<li><b>
[32:16]
TYPE
</b>[<i>read-only</i>]: Carrier type
<br>Carrier type identifier<br>1 = SPEC<br>2 = SVEC<br>3 = VFC<br>4 = SPEXI
......@@ -1026,22 +1028,27 @@ FMC0_PRES
</table>
<ul>
<li><b>
[0]
FMC0_PRES
</b>[<i>read-only</i>]: FMC 1 presence
<br>0: FMC slot 1 is populated<br>1: FMC slot 1 is not populated.
<li><b>
[1]
FMC1_PRES
</b>[<i>read-only</i>]: FMC 2 presence
<br>0: FMC slot 2 is populated<br>1: FMC slot 2 is not populated.
<li><b>
[2]
SYS_PLL_LCK
</b>[<i>read-only</i>]: System clock PLL status
<br>0: not locked<br>1: locked.
<li><b>
[3]
DDR0_CAL_DONE
</b>[<i>read-only</i>]: NOT_IMPLEMENTED: DDR3 bank 4 calibration status
<br>0: not done<br>1: done.
<li><b>
[4]
DDR1_CAL_DONE
</b>[<i>read-only</i>]: NOT_IMPLEMENTED: DDR3 bank 5 calibration status
<br>0: not done<br>1: done.
......@@ -1300,6 +1307,7 @@ FP_LEDS_MAN[7:0]
</table>
<ul>
<li><b>
[16:0]
FP_LEDS_MAN
</b>[<i>read/write</i>]: NOT_IMPLEMENTED: Front panel LED manual control
<br>NOT_IMPLEMENTED: Height front panel LED, two bits per LED.<br>00 = OFF<br>01 = Green<br>10 = Red<br>11 = Orange
......@@ -1561,10 +1569,12 @@ FMC0_N
</table>
<ul>
<li><b>
[0]
FMC0_N
</b>[<i>read/write</i>]: State of the FMC 1 reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
<li><b>
[1]
FMC1_N
</b>[<i>read/write</i>]: State of the FMC 2 reset line
<br>write 0: FMC is held in reset<br> write 1: Normal FMC operation (default)
......
This diff is collapsed.
This diff is collapsed.
`define ADDR_FFPG_STATUS 16'h0
`define FFPG_STATUS_CLOCK_INFRASTRUCTURE_BUSY_OFFSET 0
`define FFPG_STATUS_CLOCK_INFRASTRUCTURE_BUSY 32'h00000001
`define FFPG_STATUS_DAC_VCXO_BUSY_OFFSET 1
`define FFPG_STATUS_DAC_VCXO_BUSY 32'h00000002
`define FFPG_STATUS_DAC_TRIGGER_BUSY_OFFSET 2
`define FFPG_STATUS_DAC_TRIGGER_BUSY 32'h00000004
`define FFPG_STATUS_DELAY_CONFIGURATION_BUSY_OFFSET 3
`define FFPG_STATUS_DELAY_CONFIGURATION_BUSY 32'h00000008
`define FFPG_STATUS_CHANNEL_1_OE_OFFSET 4
`define FFPG_STATUS_CHANNEL_1_OE 32'h00000010
`define FFPG_STATUS_CHANNEL_2_OE_OFFSET 5
`define FFPG_STATUS_CHANNEL_2_OE 32'h00000020
`define FFPG_STATUS_CHANNEL_1_RUNNING_OFFSET 6
`define FFPG_STATUS_CHANNEL_1_RUNNING 32'h00000040
`define FFPG_STATUS_CHANNEL_2_RUNNING_OFFSET 7
`define FFPG_STATUS_CHANNEL_2_RUNNING 32'h00000080
`define FFPG_STATUS_INPUT_CLOCK_STABLE_OFFSET 8
`define FFPG_STATUS_INPUT_CLOCK_STABLE 32'h00000100
`define ADDR_FFPG_CONTROL 16'h4
`define FFPG_CONTROL_CLOCK_SELECTION_OFFSET 0
`define FFPG_CONTROL_CLOCK_SELECTION 32'h00000003
`define FFPG_CONTROL_CH1_OE_OFFSET 2
`define FFPG_CONTROL_CH1_OE 32'h00000004
`define FFPG_CONTROL_CH2_OE_OFFSET 3
`define FFPG_CONTROL_CH2_OE 32'h00000008
`define FFPG_CONTROL_CH1_MODE_OFFSET 4
`define FFPG_CONTROL_CH1_MODE 32'h00000030
`define FFPG_CONTROL_CH2_MODE_OFFSET 6
`define FFPG_CONTROL_CH2_MODE 32'h000000c0
`define FFPG_CONTROL_LED_TEST_OFFSET 8
`define FFPG_CONTROL_LED_TEST 32'h00000100
`define FFPG_CONTROL_AD9512_SYNC_OFFSET 9
`define FFPG_CONTROL_AD9512_SYNC 32'h00000200
`define FFPG_CONTROL_FINE_DELAY_ENABLE_OFFSET 10
`define FFPG_CONTROL_FINE_DELAY_ENABLE 32'h00000400
`define ADDR_FFPG_VCXO_VOLTAGE 16'h8
`define ADDR_FFPG_CLOCK_RATIO_M1 16'hc
`define ADDR_FFPG_CH1_DELAY_SET 16'h10
`define ADDR_FFPG_CH1_DELAY_RESET 16'h14
`define ADDR_FFPG_CH2_DELAY_SET 16'h18
`define ADDR_FFPG_CH2_DELAY_RESET 16'h1c
`define ADDR_FFPG_TRIGGER_THRESHOLD 16'h20
`define ADDR_FFPG_OVERFLOW 16'h24
`define ADDR_FFPG_CH1_TRIGGER_LATENCY 16'h28
`define ADDR_FFPG_FREQUENCY 16'h2c
`define ADDR_FFPG_DEBUG 16'h30
`define ADDR_FFPG_VERSION 16'h34
`define FFPG_VERSION_REVISION_OFFSET 0
`define FFPG_VERSION_REVISION 32'h00000fff
`define FFPG_VERSION_MINOR_OFFSET 12
`define FFPG_VERSION_MINOR 32'h003ff000
`define FFPG_VERSION_MAJOR_OFFSET 22
`define FFPG_VERSION_MAJOR 32'hffc00000
`define ADDR_FFPG_CH2_TRIGGER_LATENCY 16'h38
`define ADDR_FFPG_FINE_DELAY 16'h3c
`define FFPG_FINE_DELAY_VALUE_OFFSET 0
`define FFPG_FINE_DELAY_VALUE 32'h0000001f
`define FFPG_FINE_DELAY_CURRENT_OFFSET 5
`define FFPG_FINE_DELAY_CURRENT 32'h000000e0
`define FFPG_FINE_DELAY_CAPACITORS_OFFSET 8
`define FFPG_FINE_DELAY_CAPACITORS 32'h00000700
`define BASE_FFPG_CH1_SET_MEM 16'h2000
`define SIZE_FFPG_CH1_SET_MEM 32'h800
`define BASE_FFPG_CH1_RES_MEM 16'h4000
`define SIZE_FFPG_CH1_RES_MEM 32'h800
`define BASE_FFPG_CH2_SET_MEM 16'h6000
`define SIZE_FFPG_CH2_SET_MEM 32'h800
`define BASE_FFPG_CH2_RES_MEM 16'h8000
`define SIZE_FFPG_CH2_RES_MEM 32'h800
......@@ -5,4 +5,3 @@ SIM=../sim/testbench/
%:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_pkg.vhd -f html -D $(DOC)$@.htm -C $@.h -K $(SIM)$@.svh $@.wb
$(WBGEN2) -f texinfo -D $(DOC)$@.tex $@.wb
\ No newline at end of file
This diff is collapsed.
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for SVEC carrier control and status registers
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : 12/19/16 17:04:37
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity carrier_csr is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_pcb_rev_i : in std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_reserved_i : in std_logic_vector(10 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
carrier_csr_carrier_type_i : in std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC 1 presence' in reg: 'Status'
carrier_csr_stat_fmc0_pres_i : in std_logic;
-- Port for BIT field: 'FMC 2 presence' in reg: 'Status'
carrier_csr_stat_fmc1_pres_i : in std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
carrier_csr_stat_sys_pll_lck_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 4 calibration status' in reg: 'Status'
carrier_csr_stat_ddr0_cal_done_i : in std_logic;
-- Port for BIT field: 'NOT_IMPLEMENTED: DDR3 bank 5 calibration status' in reg: 'Status'
carrier_csr_stat_ddr1_cal_done_i : in std_logic;
-- Port for std_logic_vector field: 'NOT_IMPLEMENTED: Front panel LED manual control' in reg: 'Control'
carrier_csr_ctrl_fp_leds_man_o : out std_logic_vector(15 downto 0);
-- Ports for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o : out std_logic;
carrier_csr_rst_fmc0_n_i : in std_logic;
carrier_csr_rst_fmc0_n_load_o : out std_logic;
-- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o : out std_logic;
carrier_csr_rst_fmc1_n_i : in std_logic;
carrier_csr_rst_fmc1_n_load_o : out std_logic
);
end carrier_csr;
architecture syn of carrier_csr is
signal carrier_csr_ctrl_fp_leds_man_int : std_logic_vector(15 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic;
signal wr_int : std_logic;
signal rd_int : std_logic;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
carrier_csr_ctrl_fp_leds_man_int <= "0000000000000000";
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
ack_in_progress <= '0';
else
carrier_csr_rst_fmc0_n_load_o <= '0';
carrier_csr_rst_fmc1_n_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
end if;
rddata_reg(4 downto 0) <= carrier_csr_carrier_pcb_rev_i;
rddata_reg(15 downto 5) <= carrier_csr_carrier_reserved_i;
rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= carrier_csr_stat_fmc0_pres_i;
rddata_reg(1) <= carrier_csr_stat_fmc1_pres_i;
rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i;
rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i;
rddata_reg(31 downto 5) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
carrier_csr_ctrl_fp_leds_man_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= carrier_csr_ctrl_fp_leds_man_int;
rddata_reg(31 downto 16) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
carrier_csr_rst_fmc0_n_load_o <= '1';
carrier_csr_rst_fmc1_n_load_o <= '1';
end if;
rddata_reg(0) <= carrier_csr_rst_fmc0_n_i;
rddata_reg(1) <= carrier_csr_rst_fmc1_n_i;
rddata_reg(31 downto 2) <= (others => 'X');
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- NOT_IMPLEMENTED: Front panel LED manual control
carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o <= wrdata_reg(0);
-- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o <= wrdata_reg(1);
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (ack_in_progress or (wb_stb_i and wb_cyc_i));
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
`define ADDR_CARRIER_CSR_CARRIER 4'h0
`define CARRIER_CSR_CARRIER_PCB_REV_OFFSET 0
`define CARRIER_CSR_CARRIER_PCB_REV 32'h0000001f
`define CARRIER_CSR_CARRIER_RESERVED_OFFSET 5
`define CARRIER_CSR_CARRIER_RESERVED 32'h0000ffe0
`define CARRIER_CSR_CARRIER_TYPE_OFFSET 16
`define CARRIER_CSR_CARRIER_TYPE 32'hffff0000
`define ADDR_CARRIER_CSR_STAT 4'h4
`define CARRIER_CSR_STAT_FMC0_PRES_OFFSET 0
`define CARRIER_CSR_STAT_FMC0_PRES 32'h00000001
`define CARRIER_CSR_STAT_FMC1_PRES_OFFSET 1
`define CARRIER_CSR_STAT_FMC1_PRES 32'h00000002
`define CARRIER_CSR_STAT_SYS_PLL_LCK_OFFSET 2
`define CARRIER_CSR_STAT_SYS_PLL_LCK 32'h00000004
`define CARRIER_CSR_STAT_DDR0_CAL_DONE_OFFSET 3
`define CARRIER_CSR_STAT_DDR0_CAL_DONE 32'h00000008
`define CARRIER_CSR_STAT_DDR1_CAL_DONE_OFFSET 4
`define CARRIER_CSR_STAT_DDR1_CAL_DONE 32'h00000010
`define ADDR_CARRIER_CSR_CTRL 4'h8
`define CARRIER_CSR_CTRL_FP_LEDS_MAN_OFFSET 0
`define CARRIER_CSR_CTRL_FP_LEDS_MAN 32'h0000ffff
`define ADDR_CARRIER_CSR_RST 4'hc
`define CARRIER_CSR_RST_FMC0_N_OFFSET 0
`define CARRIER_CSR_RST_FMC0_N 32'h00000001
`define CARRIER_CSR_RST_FMC1_N_OFFSET 1
`define CARRIER_CSR_RST_FMC1_N 32'h00000002
......@@ -5,4 +5,3 @@ SIM=../sim/testbench/
%:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $(DOC)$@.htm -C $@.h -K $(SIM)$@.svh $@.wb
$(WBGEN2) -f texinfo -D $(DOC)$@.tex $@.wb
/*
Register definitions for slave core: SVEC carrier control and status registers
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created : 12/19/16 17:04:37
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
#define __WBGEN2_REGDEFS_CARRIER_CSR_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1ULL<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Carrier type and PCB version */
/* definitions for field: PCB revision in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_PCB_REV_MASK WBGEN2_GEN_MASK(0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_SHIFT 0
#define CARRIER_CSR_CARRIER_PCB_REV_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define CARRIER_CSR_CARRIER_PCB_REV_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: Reserved register in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_RESERVED_MASK WBGEN2_GEN_MASK(5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_SHIFT 5
#define CARRIER_CSR_CARRIER_RESERVED_W(value) WBGEN2_GEN_WRITE(value, 5, 11)
#define CARRIER_CSR_CARRIER_RESERVED_R(reg) WBGEN2_GEN_READ(reg, 5, 11)
/* definitions for field: Carrier type in reg: Carrier type and PCB version */
#define CARRIER_CSR_CARRIER_TYPE_MASK WBGEN2_GEN_MASK(16, 16)
#define CARRIER_CSR_CARRIER_TYPE_SHIFT 16
#define CARRIER_CSR_CARRIER_TYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define CARRIER_CSR_CARRIER_TYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Status */
/* definitions for field: FMC 1 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC0_PRES WBGEN2_GEN_MASK(0, 1)
/* definitions for field: FMC 2 presence in reg: Status */
#define CARRIER_CSR_STAT_FMC1_PRES WBGEN2_GEN_MASK(1, 1)
/* definitions for field: System clock PLL status in reg: Status */
#define CARRIER_CSR_STAT_SYS_PLL_LCK WBGEN2_GEN_MASK(2, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 4 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR0_CAL_DONE WBGEN2_GEN_MASK(3, 1)
/* definitions for field: NOT_IMPLEMENTED: DDR3 bank 5 calibration status in reg: Status */
#define CARRIER_CSR_STAT_DDR1_CAL_DONE WBGEN2_GEN_MASK(4, 1)
/* definitions for register: Control */
/* definitions for field: NOT_IMPLEMENTED: Front panel LED manual control in reg: Control */