- 31 Mar, 2016 2 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a, works. Did not verify simulation results
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- 30 Mar, 2016 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 16 Mar, 2016 1 commit
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Dimitris Lampridis authored
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- 04 Mar, 2016 1 commit
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Dimitris Lampridis authored
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- 24 Feb, 2016 1 commit
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Dimitris Lampridis authored
hdl: update ddr3-sp6-core pointer so that it includes the latest Manifest.py of ddr3-sp6-core without any local variables
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- 15 Feb, 2016 2 commits
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Dimitris Lampridis authored
syn: removed (and ignored) all hdlmake-generated files from SPEC and SVEC. Xilinx ISE project files could be added on official release commits if necessary
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Dimitris Lampridis authored
syn: updated Manifest.py for SPEC and SVEC to work with latest hdlmake notation for git revisions (@@) and align them with current git submodules
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- 26 Jun, 2015 1 commit
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Tomasz Wlostowski authored
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- 17 Feb, 2015 2 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
hdl: Change ddr-sp6-core module to master branch, add custom variable to select ddr copntrollers (requires hdlmake v2.1).
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- 20 Aug, 2014 3 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
The sampling frequency can't be changed dynamically in the current design. This is due to the internal fpga pll that is configured for a fixed 400MHz input.
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Matthieu Cattin authored
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- 12 May, 2014 1 commit
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Matthieu Cattin authored
- Rename folders with shorter names. - Remove documents un-related to gateware (e.g. board design).
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- 07 May, 2014 1 commit
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Matthieu Cattin authored
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- 25 Apr, 2014 5 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
- fixed and variable saturation blocks merged into one. - registers added before the crossbar in the fmc-adc mezzanine component. - acq_config_ok signal is now registered.
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Matthieu Cattin authored
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- 24 Mar, 2014 1 commit
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Matthieu Cattin authored
It was creating a big multiplexer in the wishbone crossbar and violating timing constrains. Those reserved fields are replaced by "don't care" -> better optimised during synthesis.
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- 21 Mar, 2014 1 commit
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Matthieu Cattin authored
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- 20 Mar, 2014 2 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
- Variable data saturation. - Optional trigger threshold detection deglitch filter. - Internal trigger test mode. - Sampling frequency counter. - Remaining shot counter. - Defined DAC (for VCXO) control outputs value. - Check number of samples in multi-shot (shouldn't exceed ram depth).
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- 11 Mar, 2014 1 commit
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Matthieu Cattin authored
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- 04 Mar, 2014 2 commits
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Matthieu Cattin authored
hdl: Add spexi top hdl design (Note that it's not compliant to the latest architecture and gnum core, yet).
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Matthieu Cattin authored
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- 17 Feb, 2014 1 commit
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Matthieu Cattin authored
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- 07 Feb, 2014 1 commit
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Matthieu Cattin authored
The new GN4124 core version implements a timeout and ERR treatment on the csr wishbone interface.
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- 30 Jan, 2014 1 commit
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Matthieu Cattin authored
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- 28 Jan, 2014 1 commit
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Matthieu Cattin authored
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- 17 Jan, 2014 5 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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- 16 Jan, 2014 1 commit
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Matthieu Cattin authored
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