v5.0.0.rc6   Fix the Id table

v5.0.0.rc5   FMC ADC 100M 14bit 4 channel v5.0.0 release candidate 5

wrtd-v1.0.0

fmc-adc-100m-4.1.1

v5.0.0.beta3   Changes: - minor fixes - use SPDX

v5.0.0.beta2   Added: - Calibration data from user

v5-beta2   v5-beta2 - zero offset calculation - allow users to overwrite run-time calibration data - chage offset unit from mv to uV - SDB find device fix

fmc-adc-v5.0rc3

v5-beta1

fmc-adc-100m-4.1   driver compatible with gateware 4.1

svec-fmc-adc-v4.1   FmcAdc100M14b4cha SVEC gateware release 4.1 Changelog: - Bug #1299: hdl: dpram0 erroneously instantiates dual clock memory - Feature #937: hdl - Remaining shot register in single-shot mode - Feature #1266: Increase on-chip memory for multi-shot acquisitions - Feature #1290: Replace "decimation" with "under-sampling" - Feature #1297: Clean up and update build process - Feature #1298: Clean up and update simulations and testbenches

spec-fmc-adc-v4.1   FmcAdc100M14b4cha SPEC gateware release 4.1 Changelog: - Bug #1299: hdl: dpram0 erroneously instantiates dual clock memory - Feature #937: hdl - Remaining shot register in single-shot mode - Feature #1266: Increase on-chip memory for multi-shot acquisitions - Feature #1290: Replace "decimation" with "under-sampling" - Feature #1297: Clean up and update build process - Feature #1298: Clean up and update simulations and testbenches

fmc-adc-100m-sw-2015-02   DMA from ZIO, tools improvements, minor fixes

fmc-adc-100m-sw-2014-09

fmc-adc-100m-sw-2014-05   release 2014-05

svec-fmc-adc-v4.0   FmcAdc100M14b4cha svec firmware release 4.0 Changelog: - Update VME64x core (resize A24 address mask to 0.5MB). - Add shot counter. - Add sampling frequency counter. - Check number of samples in multishot (prevent acq start if bigegr than multishot dpram). - Add programmable glitch filter to threshold detection (internal hardware trigger). - Add internal hardware trigger debug mode (to help threshold glitch filter setup). - Make ADC data saturation level programmable.

spec-fmc-adc-v4.0   FmcAdc100M14b4cha spec firmware release 4.0 Changelog: - Update GN4124 core (don't hang on unmapped wishbone address read). - Add shot counter. - Add sampling frequency counter. - Check number of samples in multishot (prevent acq start if bigegr than multishot dpram). - Add programmable glitch filter to threshold detection (internal hardware trigger). - Add internal hardware trigger debug mode (to help threshold glitch filter setup). - Make ADC data saturation level programmable.

fmc-adc-100m-sw-2014-04   production release

svec-fmc-adc-v3.0   FmcAdc100M14b4cha svec firmware release 3.0 Changelog: - Increase decimation register width from 16 to 32 bits. - Change interrupt scheme, now uses eic + vic (changes in memory map). - Insert trigger time-tag in data, after post-trigger samples. - Fix sdb bridge offset address. - Prevent acquisition start if post trigger samples or number of shots is 0 (new "acq config ok" flag). - Change trigger position register to byte-address (was sample-address). - Add non-null meta field for timetags (mainly for test). - Move fmc eic and timetag core to mezzanine (behind the wb bridge). - Map 4kb on Wishbone bus for 'DDR data' slave (to allow for VME block access).

spec-fmc-adc-v3.0   FmcAdc100M14b4cha spec gateware release 3.0 Changelog: - Increase decimation register width from 16 to 32 bits. - Change interrupt scheme, now uses eic + vic (changes in memory map). - Insert trigger time-tag in data, after post-trigger samples. - Fix sdb bridge offset address. - Prevent acquisition start if post trigger samples or number of shots is 0 (new "acq config ok" flag). - Change trigger position register to byte-address (was sample-address). - Add non-null meta field for timetags (mainly for test). - Move fmc eic and timetag core to mezzanine (behind the wb bridge).