svec-fmc-adc-v4.0   FmcAdc100M14b4cha svec firmware release 4.0 Changelog: - Update VME64x core (resize A24 address mask to 0.5MB). - Add shot counter. - Add sampling frequency counter. - Check number of samples in multishot (prevent acq start if bigegr than multishot dpram). - Add programmable glitch filter to threshold detection (internal hardware trigger). - Add internal hardware trigger debug mode (to help threshold glitch filter setup). - Make ADC data saturation level programmable.

spec-fmc-adc-v4.0   FmcAdc100M14b4cha spec firmware release 4.0 Changelog: - Update GN4124 core (don't hang on unmapped wishbone address read). - Add shot counter. - Add sampling frequency counter. - Check number of samples in multishot (prevent acq start if bigegr than multishot dpram). - Add programmable glitch filter to threshold detection (internal hardware trigger). - Add internal hardware trigger debug mode (to help threshold glitch filter setup). - Make ADC data saturation level programmable.

svec-fmc-adc-v3.0   FmcAdc100M14b4cha svec firmware release 3.0 Changelog: - Increase decimation register width from 16 to 32 bits. - Change interrupt scheme, now uses eic + vic (changes in memory map). - Insert trigger time-tag in data, after post-trigger samples. - Fix sdb bridge offset address. - Prevent acquisition start if post trigger samples or number of shots is 0 (new "acq config ok" flag). - Change trigger position register to byte-address (was sample-address). - Add non-null meta field for timetags (mainly for test). - Move fmc eic and timetag core to mezzanine (behind the wb bridge). - Map 4kb on Wishbone bus for 'DDR data' slave (to allow for VME block access).

spec-fmc-adc-v3.0   FmcAdc100M14b4cha spec gateware release 3.0 Changelog: - Increase decimation register width from 16 to 32 bits. - Change interrupt scheme, now uses eic + vic (changes in memory map). - Insert trigger time-tag in data, after post-trigger samples. - Fix sdb bridge offset address. - Prevent acquisition start if post trigger samples or number of shots is 0 (new "acq config ok" flag). - Change trigger position register to byte-address (was sample-address). - Add non-null meta field for timetags (mainly for test). - Move fmc eic and timetag core to mezzanine (behind the wb bridge).

svec-fmc-adc-v1.0   FmcAdc100M14b4cha svec firmware release 1.0 Initial release for two fmc-adc on svec.

spec-fmc-adc-v2.0   FmcAdc100M14b4cha firmware release 2.0 Changelog: - Fix bug in pre/post_trig_done signals generation. - Update wbgen wishbone interfaces (port name change). - Change utc core name into timetag core. - Takes the adc data for trigger threshold after offset/gain correction block. - Move mezzanine related wb cores to a separate module. - Rename top level fmc slot ports to be compatible with the svec (2 fmc slots). - Change spec mapping to fit the svec mapping. - Change serdes pll feedback. - Add a software reset register to reset the mezzanine related cores. - [ddr core] Fix wishbone interface to ignore stb if cyc is '0'.

spec-fmc-adc-v1.1   FmcAdc100M14b4cha firmware release 1.1 Changelog: - Fix bug in interrupt controller. - Fix bug in ddr controller (ddr3-sp6-core repo).

spec-fmc-adc-v1.0   FmcAdc100M14b4cha firmware release 1.0