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FMC ADC 100M 14b 4cha
Commits
d6208778
Commit
d6208778
authored
Jan 16, 2014
by
Matthieu Cattin
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hdl: Make mezzanine reset inactive by default on the svec.
parent
f48f3593
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6 changed files
with
154 additions
and
36 deletions
+154
-36
carrier_csr.vhd
hdl/svec/rtl/carrier_csr.vhd
+19
-13
svec_top_fmc_adc_100Ms.vhd
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+55
-14
svec_top_fmc_adc_100Ms.ucf
hdl/svec/svec_top_fmc_adc_100Ms.ucf
+3
-2
carrier_csr.h
hdl/svec/wb_gen/carrier_csr.h
+1
-1
carrier_csr.htm
hdl/svec/wb_gen/carrier_csr.htm
+70
-2
carrier_csr.wb
hdl/svec/wb_gen/carrier_csr.wb
+6
-4
No files found.
hdl/svec/rtl/carrier_csr.vhd
View file @
d6208778
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created :
Fri Jul 26 16:40:36 2013
-- Created :
Tue Jan 14 12:04:45 2014
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
@@ -49,10 +49,14 @@ entity carrier_csr is
carrier_csr_ctrl_fp_leds_man_o
:
out
std_logic_vector
(
15
downto
0
);
-- Port for std_logic_vector field: 'Reserved' in reg: 'Control'
carrier_csr_ctrl_reserved_o
:
out
std_logic_vector
(
15
downto
0
);
-- Port for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
-- Port
s
for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_o
:
out
std_logic
;
-- Port for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc0_n_i
:
in
std_logic
;
carrier_csr_rst_fmc0_n_load_o
:
out
std_logic
;
-- Ports for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
carrier_csr_rst_fmc1_n_o
:
out
std_logic
;
carrier_csr_rst_fmc1_n_i
:
in
std_logic
;
carrier_csr_rst_fmc1_n_load_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'Reserved' in reg: 'Reset Register'
carrier_csr_rst_reserved_o
:
out
std_logic_vector
(
29
downto
0
)
);
...
...
@@ -62,8 +66,6 @@ architecture syn of carrier_csr is
signal
carrier_csr_ctrl_fp_leds_man_int
:
std_logic_vector
(
15
downto
0
);
signal
carrier_csr_ctrl_reserved_int
:
std_logic_vector
(
15
downto
0
);
signal
carrier_csr_rst_fmc0_n_int
:
std_logic
;
signal
carrier_csr_rst_fmc1_n_int
:
std_logic
;
signal
carrier_csr_rst_reserved_int
:
std_logic_vector
(
29
downto
0
);
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -94,8 +96,8 @@ begin
rddata_reg
<=
"00000000000000000000000000000000"
;
carrier_csr_ctrl_fp_leds_man_int
<=
"0000000000000000"
;
carrier_csr_ctrl_reserved_int
<=
"0000000000000000"
;
carrier_csr_rst_fmc0_n_
int
<=
'0'
;
carrier_csr_rst_fmc1_n_
int
<=
'0'
;
carrier_csr_rst_fmc0_n_
load_o
<=
'0'
;
carrier_csr_rst_fmc1_n_
load_o
<=
'0'
;
carrier_csr_rst_reserved_int
<=
"000000000000000000000000000000"
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
...
...
@@ -103,8 +105,12 @@ begin
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
carrier_csr_rst_fmc0_n_load_o
<=
'0'
;
carrier_csr_rst_fmc1_n_load_o
<=
'0'
;
ack_in_progress
<=
'0'
;
else
carrier_csr_rst_fmc0_n_load_o
<=
'0'
;
carrier_csr_rst_fmc1_n_load_o
<=
'0'
;
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
...
...
@@ -139,12 +145,12 @@ begin
ack_in_progress
<=
'1'
;
when
"11"
=>
if
(
wb_we_i
=
'1'
)
then
carrier_csr_rst_fmc0_n_
int
<=
wrdata_reg
(
0
)
;
carrier_csr_rst_fmc1_n_
int
<=
wrdata_reg
(
1
)
;
carrier_csr_rst_fmc0_n_
load_o
<=
'1'
;
carrier_csr_rst_fmc1_n_
load_o
<=
'1'
;
carrier_csr_rst_reserved_int
<=
wrdata_reg
(
31
downto
2
);
end
if
;
rddata_reg
(
0
)
<=
carrier_csr_rst_fmc0_n_i
nt
;
rddata_reg
(
1
)
<=
carrier_csr_rst_fmc1_n_i
nt
;
rddata_reg
(
0
)
<=
carrier_csr_rst_fmc0_n_i
;
rddata_reg
(
1
)
<=
carrier_csr_rst_fmc1_n_i
;
rddata_reg
(
31
downto
2
)
<=
carrier_csr_rst_reserved_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
...
...
@@ -175,9 +181,9 @@ begin
-- Reserved
carrier_csr_ctrl_reserved_o
<=
carrier_csr_ctrl_reserved_int
;
-- State of the FMC 1 reset line
carrier_csr_rst_fmc0_n_o
<=
carrier_csr_rst_fmc0_n_int
;
carrier_csr_rst_fmc0_n_o
<=
wrdata_reg
(
0
)
;
-- State of the FMC 2 reset line
carrier_csr_rst_fmc1_n_o
<=
carrier_csr_rst_fmc1_n_int
;
carrier_csr_rst_fmc1_n_o
<=
wrdata_reg
(
1
)
;
-- Reserved
carrier_csr_rst_reserved_o
<=
carrier_csr_rst_reserved_int
;
rwaddr_reg
<=
wb_adr_i
;
...
...
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @
d6208778
...
...
@@ -274,7 +274,11 @@ architecture rtl of svec_top_fmc_adc_100Ms is
carrier_csr_ctrl_fp_leds_man_o
:
out
std_logic_vector
(
15
downto
0
);
carrier_csr_ctrl_reserved_o
:
out
std_logic_vector
(
15
downto
0
);
carrier_csr_rst_fmc0_n_o
:
out
std_logic
;
carrier_csr_rst_fmc0_n_i
:
in
std_logic
;
carrier_csr_rst_fmc0_n_load_o
:
out
std_logic
;
carrier_csr_rst_fmc1_n_o
:
out
std_logic
;
carrier_csr_rst_fmc1_n_i
:
in
std_logic
;
carrier_csr_rst_fmc1_n_load_o
:
out
std_logic
;
carrier_csr_rst_reserved_o
:
out
std_logic_vector
(
29
downto
0
)
);
end
component
carrier_csr
;
...
...
@@ -435,18 +439,24 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal
ddr_clk_buf
:
std_logic
;
-- Reset
signal
powerup_reset_cnt
:
unsigned
(
7
downto
0
)
:
=
"00000000"
;
signal
powerup_rst_n
:
std_logic
:
=
'0'
;
signal
sys_rst_n
:
std_logic
;
signal
ddr_rst_n
:
std_logic
;
signal
sw_rst_fmc0_n
:
std_logic
;
signal
sw_rst_fmc1_n
:
std_logic
;
signal
ddr_sw_rst_fmc0_n
:
std_logic
;
signal
ddr_sw_rst_fmc1_n
:
std_logic
;
signal
fmc0_rst_n
:
std_logic
;
signal
fmc1_rst_n
:
std_logic
;
signal
fmc0_ddr_rst_n
:
std_logic
;
signal
fmc1_ddr_rst_n
:
std_logic
;
signal
powerup_reset_cnt
:
unsigned
(
7
downto
0
)
:
=
"00000000"
;
signal
powerup_rst_n
:
std_logic
:
=
'0'
;
signal
sys_rst_n
:
std_logic
;
signal
ddr_rst_n
:
std_logic
;
signal
sw_rst_fmc0_n
:
std_logic
:
=
'1'
;
signal
sw_rst_fmc0_n_o
:
std_logic
;
signal
sw_rst_fmc0_n_i
:
std_logic
;
signal
sw_rst_fmc0_n_load
:
std_logic
;
signal
sw_rst_fmc1_n
:
std_logic
:
=
'1'
;
signal
sw_rst_fmc1_n_o
:
std_logic
;
signal
sw_rst_fmc1_n_i
:
std_logic
;
signal
sw_rst_fmc1_n_load
:
std_logic
;
signal
ddr_sw_rst_fmc0_n
:
std_logic
;
signal
ddr_sw_rst_fmc1_n
:
std_logic
;
signal
fmc0_rst_n
:
std_logic
;
signal
fmc1_rst_n
:
std_logic
;
signal
fmc0_ddr_rst_n
:
std_logic
;
signal
fmc1_ddr_rst_n
:
std_logic
;
-- VME
signal
vme_data_b_out
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -852,8 +862,12 @@ begin
carrier_csr_stat_reserved_i
=>
(
others
=>
'0'
),
carrier_csr_ctrl_fp_leds_man_o
=>
led_state_man
,
carrier_csr_ctrl_reserved_o
=>
open
,
carrier_csr_rst_fmc0_n_o
=>
sw_rst_fmc0_n
,
carrier_csr_rst_fmc1_n_o
=>
sw_rst_fmc1_n
,
carrier_csr_rst_fmc0_n_o
=>
sw_rst_fmc0_n_o
,
carrier_csr_rst_fmc0_n_i
=>
sw_rst_fmc0_n_i
,
carrier_csr_rst_fmc0_n_load_o
=>
sw_rst_fmc0_n_load
,
carrier_csr_rst_fmc1_n_o
=>
sw_rst_fmc1_n_o
,
carrier_csr_rst_fmc1_n_i
=>
sw_rst_fmc1_n_i
,
carrier_csr_rst_fmc1_n_load_o
=>
sw_rst_fmc1_n_load
,
carrier_csr_rst_reserved_o
=>
open
);
...
...
@@ -863,6 +877,33 @@ begin
cnx_master_in
(
c_WB_SLAVE_SVEC_CSR
)
.
stall
<=
'0'
;
cnx_master_in
(
c_WB_SLAVE_SVEC_CSR
)
.
int
<=
'0'
;
-- external software reset registers (to assign a non-zero default value)
p_sw_rst_fmc0
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
sys_rst_n
=
'0'
then
sw_rst_fmc0_n
<=
'1'
;
elsif
sw_rst_fmc0_n_load
=
'1'
then
sw_rst_fmc0_n
<=
sw_rst_fmc0_n_o
;
end
if
;
end
if
;
end
process
p_sw_rst_fmc0
;
sw_rst_fmc0_n_i
<=
sw_rst_fmc0_n
;
p_sw_rst_fmc1
:
process
(
sys_clk_125
)
begin
if
rising_edge
(
sys_clk_125
)
then
if
sys_rst_n
=
'0'
then
sw_rst_fmc1_n
<=
'1'
;
elsif
sw_rst_fmc1_n_load
=
'1'
then
sw_rst_fmc1_n
<=
sw_rst_fmc1_n_o
;
end
if
;
end
if
;
end
process
p_sw_rst_fmc1
;
sw_rst_fmc1_n_i
<=
sw_rst_fmc1_n
;
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
------------------------------------------------------------------------------
...
...
hdl/svec/svec_top_fmc_adc_100Ms.ucf
View file @
d6208778
...
...
@@ -952,8 +952,9 @@ NET "cmp_sync_ddr_rst/sync2" TIG;
NET "cmp_sync_fmc0_rst/sync2" TIG;
NET "cmp_sync_fmc1_rst/sync2" TIG;
NET "powerup_rst_n" TIG;
NET "cmp_carrier_csr/carrier_csr_rst_fmc0_n_int" TIG;
NET "cmp_carrier_csr/carrier_csr_rst_fmc1_n_int" TIG;
NET "sw_rst_fmc0_n" TIG;
NET "sw_rst_fmc1_n" TIG;
# DDR3
...
...
hdl/svec/wb_gen/carrier_csr.h
View file @
d6208778
...
...
@@ -3,7 +3,7 @@
* File : carrier_csr.h
* Author : auto-generated by wbgen2 from carrier_csr.wb
* Created :
Fri Jul 26 16:40:36 2013
* Created :
Tue Jan 14 12:04:45 2014
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
...
...
hdl/svec/wb_gen/carrier_csr.htm
View file @
d6208778
...
...
@@ -461,6 +461,40 @@ carrier_csr_rst_fmc0_n_o
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_fmc0_n_i
</td>
<td
class=
"td_arrow_right"
>
←
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_fmc0_n_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_fmc1_n_o
...
...
@@ -478,6 +512,40 @@ carrier_csr_rst_fmc1_n_o
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_fmc1_n_i
</td>
<td
class=
"td_arrow_right"
>
←
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_fmc1_n_load_o
</td>
<td
class=
"td_arrow_right"
>
→
</td>
</tr>
<tr>
<td
class=
"td_arrow_left"
>
</td>
<td
class=
"td_pblock_left"
>
</td>
<td
class=
"td_sym_center"
>
</td>
<td
class=
"td_pblock_right"
>
carrier_csr_rst_reserved_o[29:0]
...
...
@@ -1554,11 +1622,11 @@ FMC0_N
<li><b>
FMC0_N
</b>
[
<i>
read/write
</i>
]: State of the FMC 1 reset line
<br>
write 0: FMC is held in reset
<br>
write 1: Normal FMC operation
<br>
write 0: FMC is held in reset
<br>
write 1: Normal FMC operation
(default)
<li><b>
FMC1_N
</b>
[
<i>
read/write
</i>
]: State of the FMC 2 reset line
<br>
write 0: FMC is held in reset
<br>
write 1: Normal FMC operation
<br>
write 0: FMC is held in reset
<br>
write 1: Normal FMC operation
(default)
<li><b>
RESERVED
</b>
[
<i>
read/write
</i>
]: Reserved
...
...
hdl/svec/wb_gen/carrier_csr.wb
View file @
d6208778
...
...
@@ -133,23 +133,25 @@ peripheral {
field {
name = "State of the FMC 1 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation";
write 1: Normal FMC operation
(default)
";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc0_n";
access_bus = READ_WRITE;
access_dev = READ_
ONLY
;
access_dev = READ_
WRITE
;
};
field {
name = "State of the FMC 2 reset line";
description = "write 0: FMC is held in reset\
write 1: Normal FMC operation";
write 1: Normal FMC operation
(default)
";
type = BIT;
load = LOAD_EXT;
size = 1;
prefix = "fmc1_n";
access_bus = READ_WRITE;
access_dev = READ_
ONLY
;
access_dev = READ_
WRITE
;
};
field {
...
...
Write
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