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FMC ADC 100M 14b 4cha
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FMC ADC 100M 14b 4cha
Commits
471d64b3
Commit
471d64b3
authored
Apr 25, 2014
by
Matthieu Cattin
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syn: svec-fmc-adc gateware release 4.0
parent
ad1db4c2
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6 changed files
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3800 additions
and
3268 deletions
+3800
-3268
sdb_meta_pkg.vhd
hdl/svec/rtl/sdb_meta_pkg.vhd
+4
-4
svec_fmc_adc_100Ms.xise
hdl/svec/syn/svec_fmc_adc_100Ms.xise
+99
-99
svec_top_fmc_adc_100Ms.par
hdl/svec/syn/svec_top_fmc_adc_100Ms.par
+93
-85
svec_top_fmc_adc_100Ms.syr
hdl/svec/syn/svec_top_fmc_adc_100Ms.syr
+1880
-1469
svec_top_fmc_adc_100Ms.twr
hdl/svec/syn/svec_top_fmc_adc_100Ms.twr
+1674
-1577
svec_top_fmc_adc_100Ms_map.mrp
hdl/svec/syn/svec_top_fmc_adc_100Ms_map.mrp
+50
-34
No files found.
hdl/svec/rtl/sdb_meta_pkg.vhd
View file @
471d64b3
...
...
@@ -54,13 +54,13 @@ package sdb_meta_pkg is
syn_module_name
=>
"svec_top_fmc_adc"
,
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id
=>
"
3f94d996746574776e3cf47cdb473a35
"
,
syn_commit_id
=>
"
26749f0a1873c215abb33942a8a335db
"
,
-- Synthesis tool name (string, 8 char)
syn_tool_name
=>
"ISE "
,
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version
=>
x"00000133"
,
-- Synthesis date (bcd encoded, 32-bit, yyyymmdd)
syn_date
=>
x"20140
116
"
,
syn_date
=>
x"20140
425
"
,
-- Synthesised by (string, 15 char)
syn_username
=>
"mcattin "
);
...
...
@@ -69,8 +69,8 @@ package sdb_meta_pkg is
product
=>
(
vendor_id
=>
x"000000000000CE42"
,
-- CERN
device_id
=>
x"5c01a632"
,
-- echo "svec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version
=>
x"000
3
0000"
,
-- bcd encoded, [31:16] = major, [15:0] = minor
date
=>
x"20140
116
"
,
-- yyyymmdd
version
=>
x"000
4
0000"
,
-- bcd encoded, [31:16] = major, [15:0] = minor
date
=>
x"20140
425
"
,
-- yyyymmdd
name
=>
"svec_fmcadc100m14b "
));
...
...
hdl/svec/syn/svec_fmc_adc_100Ms.xise
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471d64b3
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hdl/svec/syn/svec_top_fmc_adc_100Ms.par
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471d64b3
This diff is collapsed.
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hdl/svec/syn/svec_top_fmc_adc_100Ms.syr
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471d64b3
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hdl/svec/syn/svec_top_fmc_adc_100Ms.twr
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471d64b3
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hdl/svec/syn/svec_top_fmc_adc_100Ms_map.mrp
View file @
471d64b3
...
...
@@ -11,46 +11,46 @@ Target Device : xc6slx150t
Target Package : fgg900
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date :
Thu Jan 16 18:35:40
2014
Mapped Date :
Fri Apr 25 16:36:58
2014
Design Summary
--------------
Number of errors: 0
Number of warnings: 7
Slice Logic Utilization:
Number of Slice Registers: 9,
051 out of 184,304 4
%
Number used as Flip Flops: 9,
051
Number of Slice Registers: 9,
485 out of 184,304 5
%
Number used as Flip Flops: 9,
427
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics:
0
Number of Slice LUTs: 11,
186
out of 92,152 12%
Number used as logic: 1
0,781 out of 92,152 11
%
Number using O6 output only: 8,
189
Number using O5 output only:
317
Number using O5 and O6: 2,
275
Number used as AND/OR logics:
58
Number of Slice LUTs: 11,
668
out of 92,152 12%
Number used as logic: 1
1,397 out of 92,152 12
%
Number using O6 output only: 8,
207
Number using O5 output only:
403
Number using O5 and O6: 2,
787
Number used as ROM: 0
Number used as Memory:
13
out of 21,680 1%
Number used as Memory:
77
out of 21,680 1%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register:
13
Number used as Shift Register:
77
Number using O6 output only: 5
Number using O5 output only: 0
Number using O5 and O6:
8
Number used exclusively as route-thrus:
392
Number with same-slice register load:
373
Number with same-slice carry load:
19
Number using O5 and O6:
72
Number used exclusively as route-thrus:
194
Number with same-slice register load:
172
Number with same-slice carry load:
22
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 4,
219 out of 23,038 18
%
Nummber of MUXCYs used: 2,
224 out of 46,076 4
%
Number of LUT Flip Flop pairs used: 13,
002
Number with an unused Flip Flop:
4,961 out of 13,002
38%
Number with an unused LUT:
1,816 out of 13,002 13
%
Number of fully used LUT-FF pairs: 6,
225 out of 13,002 47
%
Number of unique control sets: 3
42
Number of occupied Slices: 4,
581 out of 23,038 19
%
Nummber of MUXCYs used: 2,
760 out of 46,076 5
%
Number of LUT Flip Flop pairs used: 13,
878
Number with an unused Flip Flop:
5,329 out of 13,878
38%
Number with an unused LUT:
2,210 out of 13,878 15
%
Number of fully used LUT-FF pairs: 6,
339 out of 13,878 45
%
Number of unique control sets: 3
69
Number of slice register sites lost
to control set restrictions:
744
out of 184,304 1%
to control set restrictions:
808
out of 184,304 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
...
...
@@ -59,8 +59,8 @@ Slice Logic Distribution:
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 35
0 out of 540 64
%
Number of LOCed IOBs: 35
0 out of 350
100%
Number of bonded IOBs: 35
6 out of 540 65
%
Number of LOCed IOBs: 35
6 out of 356
100%
Specific Feature Utilization:
Number of RAMB16BWERs: 38 out of 268 14%
...
...
@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets:
4.06
Average Fanout of Non-Clock Nets:
3.97
Peak Memory Usage: 6
31
MB
Total REAL time to MAP completion: 7 mins
47
secs
Total CPU time to MAP completion (all processors): 8 mins
4
secs
Peak Memory Usage: 6
24
MB
Total REAL time to MAP completion: 7 mins
51
secs
Total CPU time to MAP completion (all processors): 8 mins
5
secs
Table of Contents
-----------------
...
...
@@ -127,6 +127,9 @@ Section 1 - Errors
Section 2 - Warnings
--------------------
WARNING:Security:42 - Your license support version '2014.04' for ISE expires in
4 days after which you will not qualify for Xilinx software updates or new
releases.
WARNING:MapLib:701 - Signal ddr0_zio_b connected to top level port ddr0_zio_b
has been removed.
WARNING:MapLib:701 - Signal ddr1_zio_b connected to top level port ddr1_zio_b
...
...
@@ -161,6 +164,7 @@ Section 3 - Informational
INFO:Map:284 - Map is running with the multi-threading option on. Map currently
supports the use of up to 2 processors. Based on the the user options and
machine load, Map will use 2 processors during this run.
INFO:Security:56 - Part 'xc6slx150t' is not a WebPack part.
INFO:LIT:243 - Logical network
cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b.cmp_ddr3_ctrl
/memc4_infrastructure_inst/rst0_sync_r<24> has no load.
...
...
@@ -168,10 +172,10 @@ INFO:LIT:395 - The above info message is repeated 6 more times for the following
(max. 5 shown):
cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl
/memc5_infrastructure_inst/rst0_sync_r<24>,
N18
21
,
N18
23
,
N18
27
,
N18
29
N18
03
,
N18
05
,
N18
09
,
N18
11
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
...
...
@@ -187,7 +191,7 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
6
0
block(s) removed
6
2
block(s) removed
2 block(s) optimized away
60 signal(s) removed
...
...
@@ -548,6 +552,12 @@ removed.
* Loadless block
"cmp_ddr_ctrl_bank5/cmp_ddr3_ctrl_wrapper/gen_svec_bank5_64b_32b.cmp_ddr3_ctrl/m
emc5_infrastructure_inst/syn_clk0_powerup_pll_locked" (FF) removed.
Loadless block
"cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/Madd_pre_trig_value[31]_GND_208_
o_add_67_OUT31" (ROM) removed.
Loadless block
"cmp_fmc_adc_mezzanine_1/cmp_fmc_adc_100Ms_core/Madd_pre_trig_value[31]_GND_208_
o_add_67_OUT31" (ROM) removed.
The trimmed logic reported below is either:
1. part of a cycle
...
...
@@ -825,6 +835,12 @@ Section 6 - IOB Properties
| pcbrev_i<2> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<3> | IOB | INPUT | LVCMOS25 | | | | | | |
| pcbrev_i<4> | IOB | INPUT | LVCMOS25 | | | | | | |
| pll20dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll20dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_din_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sclk_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| pll25dac_sync_n_o | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | |
| rst_n_i | IOB | INPUT | LVCMOS33 | | | | | | |
| vme_addr_b<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
| vme_addr_b<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | |
...
...
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