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Updated date
JTAG Breakout PCB for FMC PROFINET V2
fmc-profinet!2
· created
Jun 26, 2024
by
Bernard Guncic
Merged
0
updated
Jun 26, 2024
WIP: Pieter fasec wrpc v5
wr-cores!14
· created
May 10, 2024
by
Pieter Van Trappen
wrpc-v5
Merged
1
updated
Jun 13, 2024
platform/xilinx/xwrc_platform_vivado.vhd: Generate direct DMTD clock using a BUFR
wr-cores!15
· created
Jun 05, 2024
by
Frederik Pfautsch
wrpc-v5
Merged
0
updated
Jun 13, 2024
modules/wrc_core/wrc_periph.vhd: Add reset signal to sensitivity list
wr-cores!16
· created
Jun 05, 2024
by
Frederik Pfautsch
wrpc-v5
Merged
0
updated
Jun 13, 2024
platform/xilinx/vivado: Fix generates of clock signals that originate from phys
wr-cores!17
· created
Jun 05, 2024
by
Frederik Pfautsch
wrpc-v5
Merged
0
updated
Jun 13, 2024
Resolve "[Build System] Rename Docker Containers in Build Scripts"
diot-monimod!3
· created
Jun 05, 2024
by
MIchael Lettrich
bug
monimod-fantray
Merged
Approved
1
0
updated
Jun 07, 2024
Addition of board specific OID that we need to control the timing output of the…
wrpc-sw!17
· created
Apr 29, 2024
by
Konstantinos Asteriou
wrpc-v5
Merged
0
updated
May 15, 2024
Add macro-based dpram for Xilinx/AMD 7Series FPGA
general-cores!66
· created
May 02, 2024
by
Frederik Pfautsch
Merged
0
updated
May 03, 2024
gc argb led drv
general-cores!67
· created
May 03, 2024
by
Tristan Gingold
Merged
0
updated
May 03, 2024
Patch 9
tr-pexp!10
· created
Nov 07, 2023
by
Marko Levicnik
Merged
0
updated
Apr 26, 2024
add -min argument to get_property PERIOD to return the minimum value of the returned list
general-cores!65
· created
Apr 16, 2024
by
Julien Egli
Merged
0
updated
Apr 16, 2024
Fix to CDC constraints generator matching filters
general-cores!43
· created
Aug 17, 2023
by
André Pinho
Merged
1
8
updated
Mar 13, 2024
Resolve "Linux driver for wb simple uart"
general-cores!62
· created
Jan 24, 2024
by
Konstantinos Blantos
software
Merged
0
updated
Mar 11, 2024
Resolve "Would you be happy to integrate FuseSoC core files into the repo?"
urv-core!2
· created
Feb 07, 2024
by
Shareef Jalloq
Merged
1
updated
Feb 12, 2024
Resolve "Support Verilog output with gen_sourceid tool"
general-cores!63
· created
Jan 30, 2024
by
Dimitris Lampridis
Merged
1
updated
Jan 30, 2024
Resolve "add rx/tx interrupt enable in wb_uart"
general-cores!58
· created
Jan 15, 2024
by
Konstantinos Blantos
Merged
4
updated
Jan 26, 2024
Resolve "add a fifo with mixed width"
general-cores!57
· created
Dec 21, 2023
by
Tristan Gingold
Merged
1
updated
Jan 26, 2024
NVC: Add new variables for setting analysis and elaboration flags, update documentation
hdl-make!28
· created
Jan 19, 2024
by
Augusto Fraga Giachero
develop
Merged
0
updated
Jan 25, 2024
Create branch wb_axi_bridge_fix and add fix for wb - axi4 lite bridge
general-cores!60
· created
Jan 23, 2024
by
Quentin Genoud
Merged
0
updated
Jan 23, 2024
Add support to NVC simulator
hdl-make!27
· created
Jan 16, 2024
by
Augusto Fraga Giachero
develop
Merged
1
updated
Jan 17, 2024
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