- if receiving with 62.5MHz, trunkate the LSB of the received timestamp
  to ensure constant reception frequency, before, if the tx timestamp
  was odd, the data was released by the streamers full 16ns later, this
  created a jitter on reception, whem measuring the period between
  received+delayed data

- the rx timestamps where taken into account without checking whether
  they are valid, they might not be valid if the synchronization is
  not good.

based on g_pcs_16bit

Provide the rate of the WR Reference Clock based on the information
about the width of the PCS word. It is assumed to be related:
* 16bit word with 62.5MHz clock
*  8bit word with  125MHz clock

WR Streamers need to be used with WR Reference clock of 62.5MHz,
adding generic to specify what ref_clk is used (125MHz by default,
or 62.5MHz)

The generic g_ref_clk_rate was dummy, i.e. never used. The module
pulse_stamper is used with input reference clock (and tm_cycles_i)
of 125MHz and 62.5MHz clock, in the wr_streamers. Added possibility
to define what clock is used (default 125MHz or 62.5MHz). In any
case, the output timestamp is of cycle period of 8ns.

compiled from commit:
25f814a3 update ppsi to fix 1-pps generation in Master mode

PPS csync is asserted one 125MHz ref clock cycle before the actual PPS. It can be used for aligning another signal to the PPS.

platform/xilinx: add generics to Xilinx platform to select which GTP channel to use (defaults to ch1)

wrpc-sw binaries compiled from commit:
a2dd8bb9: spec_defconfig: remove spaces from built-in init script

txts -> dio_p/n_o[2] (= Lemo 3)
rxts -> dio_p/n_o[1] (= Lemo 2; formerly used for 62.5 MHz RefClk)