adding wrc_board_fased Vivado ip core constraints

767f450b · Grzegorz Daniluk · 2464c1e2 · 767f450b · 767f450b
Commit 767f450b authored Aug 17, 2017 by Grzegorz Daniluk
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Manifest.py board/fasec/Manifest.py +1 -0

wrc_board_fasec_ip.xdc board/fasec/wrc_board_fasec_ip.xdc +14 -0

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--- a/board/fasec/Manifest.py
+++ b/board/fasec/Manifest.py
@@ -2,6 +2,7 @@ files = [
    "wr_fasec_pkg.vhd",
    "xwrc_board_fasec.vhd",
    "wrc_board_fasec.vhd",
+    "wrc_board_fasec_ip.xdc"
 ]

 modules = {

--- a/board/fasec/wrc_board_fasec_ip.xdc
+++ b/board/fasec/wrc_board_fasec_ip.xdc
+create_clock -period 50.000 -name clk_20m_vcxo -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]
+create_clock -period 8.000 -name clk_125m_pllref -waveform {0.000 4.000} [get_ports clk_125m_pllref_p_i]
+create_clock -period 8.000 -name clk_125m_gtp -waveform {0.000 4.000} [get_ports clk_125m_gtp_p_i]
+create_clock -period 100.000 -name clk_10m_ext -waveform {0.000 50.000} [get_ports clk_10m_ext_i]
+create_clock -period 16.000 -name clk_gtx_rx -waveform {0.000 8.000} [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/RXOUTCLK]
+create_generated_clock -name clk_gtx_tx -source [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtp_dedicated_clk/O] -divide_by 2 [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_phy_kintex7.cmp_gtx/U_GTX_INST/gtxe2_i/TXOUTCLK]
+
+set_clock_groups -asynchronous -group [get_clocks clk_gtx_rx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+set_clock_groups -asynchronous -group [get_clocks clk_gtx_tx] -group [get_clocks [get_clocks -of_objects [get_pins cmp_xwrc_board_fasec/cmp_xwrc_platform/gen_default_plls.gen_kintex7_default_plls.cmp_dmtd_clk_pll/CLKOUT0]]]
+
+set_clock_groups -asynchronous -group [get_clocks clk_sys] -group [get_clocks clk_gtx_rx]
+
+
+