Skip to content

W
White Rabbit core collection
Commit 76741ddb authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Grzegorz Daniluk
Browse files
Options

board: expose WB aux master interface on all supported boards

parent 8b4c2d9f
Hide whitespace changes
Inline Side-by-side
Showing with 159 additions and 6 deletions
board/spec/wr_spec_pkg.vhd
View file @ 76741ddb
......@@ -71,6 +71,8 @@ package wr_spec_pkg is
flash_miso_i : in std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
......@@ -185,6 +187,18 @@ package wr_spec_pkg is
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
......
board/spec/wrc_board_spec.vhd
View file @ 76741ddb
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-03-10
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -174,6 +174,19 @@ entity wrc_board_spec is
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
......@@ -314,6 +327,9 @@ architecture std_wrapper of wrc_board_spec is
signal wb_slave_out : t_wishbone_slave_out;
signal wb_slave_in : t_wishbone_slave_in;
signal aux_master_out : t_wishbone_master_out;
signal aux_master_in : t_wishbone_master_in;
-- Etherbone interface
signal wb_eth_master_out : t_wishbone_master_out;
signal wb_eth_master_in : t_wishbone_master_in;
......@@ -349,6 +365,20 @@ begin -- architecture struct
wb_int_o <= wb_slave_out.int;
wb_dat_o <= wb_slave_out.dat;
aux_master_adr_o <= aux_master_out.adr;
aux_master_dat_o <= aux_master_out.dat;
aux_master_cyc_o <= aux_master_out.cyc;
aux_master_stb_o <= aux_master_out.stb;
aux_master_sel_o <= aux_master_out.sel;
aux_master_we_o <= aux_master_out.we;
aux_master_in.dat <= aux_master_dat_i;
aux_master_in.ack <= aux_master_ack_i;
aux_master_in.int <= aux_master_int_i;
aux_master_in.err <= aux_master_err_i;
aux_master_in.rty <= aux_master_rty_i;
aux_master_in.stall <= aux_master_stall_i;
wrf_src_adr_o <= wrf_src_out.adr;
wrf_src_dat_o <= wrf_src_out.dat;
wrf_src_cyc_o <= wrf_src_out.cyc;
......@@ -465,6 +495,8 @@ begin -- architecture struct
flash_miso_i => flash_miso_i,
wb_slave_o => wb_slave_out,
wb_slave_i => wb_slave_in,
aux_master_o => aux_master_out,
aux_master_i => aux_master_in,
wrf_src_o => wrf_src_out,
wrf_src_i => wrf_src_in,
wrf_snk_o => wrf_snk_out,
......
board/spec/xwrc_board_spec.vhd
View file @ 76741ddb
......@@ -7,7 +7,7 @@
-- Author(s) : Grzegorz Daniluk <grzegorz.daniluk@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-17
-- Last update: 2017-03-10
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -167,6 +167,9 @@ entity xwrc_board_spec is
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
......@@ -477,6 +480,8 @@ begin -- architecture struct
owr_i => onewire_in,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
aux_master_o => aux_master_o,
aux_master_i => aux_master_i,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
board/svec/wr_svec_pkg.vhd
View file @ 76741ddb
......@@ -73,6 +73,8 @@ package wr_svec_pkg is
spi_miso_i : in std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
......@@ -186,6 +188,18 @@ package wr_svec_pkg is
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
......
board/svec/wrc_board_svec.vhd
View file @ 76741ddb
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-03-10
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -176,6 +176,19 @@ entity wrc_board_svec is
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
......@@ -310,6 +323,9 @@ architecture std_wrapper of wrc_board_svec is
signal wb_slave_out : t_wishbone_slave_out;
signal wb_slave_in : t_wishbone_slave_in;
signal aux_master_out : t_wishbone_master_out;
signal aux_master_in : t_wishbone_master_in;
-- Etherbone interface
signal wb_eth_master_out : t_wishbone_master_out;
signal wb_eth_master_in : t_wishbone_master_in;
......@@ -345,6 +361,20 @@ begin -- architecture struct
wb_int_o <= wb_slave_out.int;
wb_dat_o <= wb_slave_out.dat;
aux_master_adr_o <= aux_master_out.adr;
aux_master_dat_o <= aux_master_out.dat;
aux_master_cyc_o <= aux_master_out.cyc;
aux_master_stb_o <= aux_master_out.stb;
aux_master_sel_o <= aux_master_out.sel;
aux_master_we_o <= aux_master_out.we;
aux_master_in.dat <= aux_master_dat_i;
aux_master_in.ack <= aux_master_ack_i;
aux_master_in.int <= aux_master_int_i;
aux_master_in.err <= aux_master_err_i;
aux_master_in.rty <= aux_master_rty_i;
aux_master_in.stall <= aux_master_stall_i;
wrf_src_adr_o <= wrf_src_out.adr;
wrf_src_dat_o <= wrf_src_out.dat;
wrf_src_cyc_o <= wrf_src_out.cyc;
......@@ -463,6 +493,8 @@ begin -- architecture struct
spi_miso_i => spi_miso_i,
wb_slave_o => wb_slave_out,
wb_slave_i => wb_slave_in,
aux_master_o => aux_master_out,
aux_master_i => aux_master_in,
wrf_src_o => wrf_src_out,
wrf_src_i => wrf_src_in,
wrf_snk_o => wrf_snk_out,
......
board/svec/xwrc_board_svec.vhd
View file @ 76741ddb
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-02-16
-- Last update: 2017-03-10
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -170,6 +170,9 @@ entity xwrc_board_svec is
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plainfbrc")
---------------------------------------------------------------------------
......@@ -483,6 +486,8 @@ begin -- architecture struct
owr_i => onewire_in,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
aux_master_o => aux_master_o,
aux_master_i => aux_master_i,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
board/vfchd/wr_vfchd_pkg.vhd
View file @ 76741ddb
......@@ -56,6 +56,8 @@ package wr_vfchd_pkg is
onewire_oen_o : out std_logic;
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_dummy_src_in;
wrf_snk_o : out t_wrf_sink_out;
......@@ -154,6 +156,18 @@ package wr_vfchd_pkg is
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
wrf_src_adr_o : out std_logic_vector(1 downto 0);
wrf_src_dat_o : out std_logic_vector(15 downto 0);
wrf_src_cyc_o : out std_logic;
......
board/vfchd/wrc_board_vfchd.vhd
View file @ 76741ddb
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-03-10
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -160,6 +160,19 @@ entity wrc_board_vfchd is
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
aux_master_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
aux_master_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
aux_master_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
aux_master_sel_o : out std_logic_vector(c_wishbone_address_width/8-1 downto 0);
aux_master_we_o : out std_logic;
aux_master_cyc_o : out std_logic;
aux_master_stb_o : out std_logic;
aux_master_ack_i : in std_logic := '0';
aux_master_int_i : in std_logic := '0';
aux_master_err_i : in std_logic := '0';
aux_master_rty_i : in std_logic := '0';
aux_master_stall_i : in std_logic := '0';
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
......@@ -298,6 +311,9 @@ architecture std_wrapper of wrc_board_vfchd is
signal wb_eth_master_out : t_wishbone_master_out;
signal wb_eth_master_in : t_wishbone_master_in;
signal aux_master_out : t_wishbone_master_out;
signal aux_master_in : t_wishbone_master_in;
-- Aux diagnostics
constant c_diag_ro_size : integer := g_diag_ro_vector_width/32;
constant c_diag_rw_size : integer := g_diag_rw_vector_width/32;
......@@ -329,6 +345,20 @@ begin -- architecture struct
wb_int_o <= wb_slave_out.int;
wb_dat_o <= wb_slave_out.dat;
aux_master_adr_o <= aux_master_out.adr;
aux_master_dat_o <= aux_master_out.dat;
aux_master_cyc_o <= aux_master_out.cyc;
aux_master_stb_o <= aux_master_out.stb;
aux_master_sel_o <= aux_master_out.sel;
aux_master_we_o <= aux_master_out.we;
aux_master_in.dat <= aux_master_dat_i;
aux_master_in.ack <= aux_master_ack_i;
aux_master_in.int <= aux_master_int_i;
aux_master_in.err <= aux_master_err_i;
aux_master_in.rty <= aux_master_rty_i;
aux_master_in.stall <= aux_master_stall_i;
wrf_src_adr_o <= wrf_src_out.adr;
wrf_src_dat_o <= wrf_src_out.dat;
wrf_src_cyc_o <= wrf_src_out.cyc;
......@@ -431,6 +461,8 @@ begin -- architecture struct
onewire_oen_o => onewire_oen_o,
wb_slave_o => wb_slave_out,
wb_slave_i => wb_slave_in,
aux_master_o => aux_master_out,
aux_master_i => aux_master_in,
wrf_src_o => wrf_src_out,
wrf_src_i => wrf_src_in,
wrf_snk_o => wrf_snk_out,
......
board/vfchd/xwrc_board_vfchd.vhd
View file @ 76741ddb
......@@ -7,7 +7,7 @@
-- Author(s) : Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2016-07-26
-- Last update: 2017-03-10
-- Last update: 2017-07-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level wrapper for WR PTP core including all the modules
......@@ -148,6 +148,9 @@ entity xwrc_board_vfchd is
wb_slave_o : out t_wishbone_slave_out;
wb_slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
aux_master_o : out t_wishbone_master_out;
aux_master_i : in t_wishbone_master_in := cc_dummy_master_in;
---------------------------------------------------------------------------
-- WR fabric interface (when g_fabric_iface = "plain")
---------------------------------------------------------------------------
......@@ -471,6 +474,8 @@ begin -- architecture struct
owr_i => onewire_in,
wb_slave_i => wb_slave_i,
wb_slave_o => wb_slave_o,
aux_master_o => aux_master_o,
aux_master_i => aux_master_i,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment