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7c8b5fb0
Commit
7c8b5fb0
authored
Aug 18, 2017
by
Grzegorz Daniluk
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adding tcl scripts for fasec reference design Vivado project
parent
930f334c
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build.tcl
syn/fasec_ref_design/build.tcl
+9
-0
fasec_ref_design.tcl
syn/fasec_ref_design/fasec_ref_design.tcl
+194
-0
fasec_ref_design.xdc
top/fasec_ref_design/fasec_ref_design.xdc
+72
-0
system_top.tcl
top/fasec_ref_design/system_top.tcl
+1413
-0
No files found.
syn/fasec_ref_design/build.tcl
0 → 100644
View file @
7c8b5fb0
# Create Vivado project
source
./fasec_ref_design.tcl
# Create block design
source
../../top/fasec_ref_design/system_top.tcl
# Generate the wrapper
set
design_name
[
get_bd_designs
]
make_wrapper -files
[
get_files
$design
_name.bd
]
-top -import
syn/fasec_ref_design/fasec_ref_design.tcl
0 → 100644
View file @
7c8b5fb0
#
# Vivado (TM
)
v2016.4
(
64-bit
)
#
# fasec_ref_design.tcl: Tcl script for re-creating project 'fasec_ref_design'
#
# Generated by Vivado on Fri Aug 18 11:05:12 CEST 2017
# IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (fasec_ref_design.tcl
)
that was generated.
#
# 2. The following source(s
)
files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script
)
#
# <none>
#
# 3. The following remote source files that were added to the original project:-
#
# "/home/greg/wr/wr-cores/top/fasec_ref_design/fasec_ref_design.xdc"
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path
)
set
origin_dir
"."
# Use origin directory path location variable, if specified in the tcl shell
if
{
[
info
exists ::origin_dir_loc
]
}
{
set origin_dir
$::origin
_dir_loc
}
variable
script_file
set
script_file
"fasec_ref_design.tcl"
# Help information for this script
proc
help
{}
{
variable script_file
puts
"
\n
Description:"
puts
"Recreate a Vivado project from this script. The created project will be"
puts
"functionally equivalent to the original project for which this script was"
puts
"generated. The script contains commands for creating a project, filesets,"
puts
"runs, adding/importing sources and setting properties on various objects.
\n
"
puts
"Syntax:"
puts
"
$script
_file"
puts
"
$script
_file -tclargs
\[
--origin_dir <path>
\]
"
puts
"
$script
_file -tclargs
\[
--help
\]\n
"
puts
"Usage:"
puts
"Name Description"
puts
"-------------------------------------------------------------------------"
puts
"
\[
--origin_dir <path>
\]
Determine source file paths wrt this path. Default"
puts
" origin_dir path value is
\"
.
\"
, otherwise, the value"
puts
" that was set with the
\"
-paths_relative_to
\"
switch"
puts
" when this script was generated.
\n
"
puts
"
\[
--help
\]
Print help information for this script"
puts
"-------------------------------------------------------------------------
\n
"
exit 0
}
if
{
$::argc
> 0
}
{
for
{
set
i 0
}
{
$i
<
[
llength
$::argc
]}
{
incr
i
}
{
set option
[
string
trim
[
lindex
$::argv
$i
]]
switch -regexp --
$option
{
"--origin_dir"
{
incr i
;
set origin_dir
[
lindex
$::argv
$i
]
}
"--help"
{
help
}
default
{
if
{
[
regexp
{
^-
}
$option
]
}
{
puts
"ERROR: Unknown option '
$option
' specified, please type '
$script
_file -tclargs --help' for usage info.
\n
"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set
orig_proj_dir
"
[
file
normalize
"
$origin
_dir/"
]
"
# Create project
create_project fasec_ref_design . -part xc7z030ffg676-2
# Set the directory path for the new project
set
proj_dir
[
get_property directory
[
current_project
]]
# Reconstruct message rules
# None
# Set project properties
set
obj
[
get_projects fasec_ref_design
]
set_property
"corecontainer.enable"
"1"
$obj
set_property
"default_lib"
"xil_defaultlib"
$obj
set_property
"ip_cache_permissions"
"read write"
$obj
set_property
"ip_output_repo"
"/home/greg/wr/wr-cores/syn/fasec_ref_design/fasec_ref_design.cache/ip"
$obj
set_property
"part"
"xc7z030ffg676-2"
$obj
set_property
"sim.ip.auto_export_scripts"
"1"
$obj
set_property
"simulator_language"
"Mixed"
$obj
set_property
"target_language"
"VHDL"
$obj
set_property
"xsim.array_display_limit"
"64"
$obj
set_property
"xsim.trace_limit"
"65536"
$obj
# Create 'sources_1' fileset (if not found
)
if
{[
string
equal
[
get_filesets -quiet sources_1
]
""
]}
{
create_fileset -srcset sources_1
}
# Set IP repository paths
set
obj
[
get_filesets sources_1
]
set_property
"ip_repo_paths"
"
[
file
normalize
"
$origin
_dir/../../"
]
"
$obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set
obj
[
get_filesets sources_1
]
# Empty (no sources present
)
# Set 'sources_1' fileset properties
set
obj
[
get_filesets sources_1
]
# Create 'constrs_1' fileset (if not found
)
if
{[
string
equal
[
get_filesets -quiet constrs_1
]
""
]}
{
create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
set
obj
[
get_filesets constrs_1
]
# Add/Import constrs file and set constrs file properties
set
file
"
[
file
normalize
"
$origin
_dir/../../top/fasec_ref_design/fasec_ref_design.xdc"
]
"
set
file_added
[
add_files -norecurse -fileset
$obj
$file
]
set
file
"
$origin
_dir/../../top/fasec_ref_design/fasec_ref_design.xdc"
set
file
[
file
normalize
$file
]
set
file_obj
[
get_files -of_objects
[
get_filesets constrs_1
]
[
list
"*
$file
"
]]
set_property
"file_type"
"XDC"
$file
_obj
# Set 'constrs_1' fileset properties
set
obj
[
get_filesets constrs_1
]
# Create 'sim_1' fileset (if not found
)
if
{[
string
equal
[
get_filesets -quiet sim_1
]
""
]}
{
create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
set
obj
[
get_filesets sim_1
]
# Empty (no sources present
)
# Set 'sim_1' fileset properties
set
obj
[
get_filesets sim_1
]
set_property
"transport_int_delay"
"0"
$obj
set_property
"transport_path_delay"
"0"
$obj
set_property
"xelab.nosort"
"1"
$obj
set_property
"xelab.unifast"
""
$obj
# Create 'synth_1' run (if not found
)
if
{[
string
equal
[
get_runs -quiet synth_1
]
""
]}
{
create_run -name synth_1 -part xc7z030ffg676-2 -flow
{
Vivado Synthesis 2016
}
-strategy
"Vivado Synthesis Defaults"
-constrset constrs_1
}
else
{
set_property strategy
"Vivado Synthesis Defaults"
[
get_runs synth_1
]
set_property flow
"Vivado Synthesis 2016"
[
get_runs synth_1
]
}
set
obj
[
get_runs synth_1
]
set_property
"needs_refresh"
"1"
$obj
set_property
"part"
"xc7z030ffg676-2"
$obj
# set the current synth run
current_run -synthesis
[
get_runs synth_1
]
# Create 'impl_1' run (if not found
)
if
{[
string
equal
[
get_runs -quiet impl_1
]
""
]}
{
create_run -name impl_1 -part xc7z030ffg676-2 -flow
{
Vivado Implementation 2016
}
-strategy
"Vivado Implementation Defaults"
-constrset constrs_1 -parent_run synth_1
}
else
{
set_property strategy
"Vivado Implementation Defaults"
[
get_runs impl_1
]
set_property flow
"Vivado Implementation 2016"
[
get_runs impl_1
]
}
set
obj
[
get_runs impl_1
]
set_property
"needs_refresh"
"1"
$obj
set_property
"part"
"xc7z030ffg676-2"
$obj
set_property
"steps.write_bitstream.args.readback_file"
"0"
$obj
set_property
"steps.write_bitstream.args.verbose"
"0"
$obj
# set the current impl run
current_run -implementation
[
get_runs impl_1
]
puts
"INFO: Project created:fasec_ref_design"
top/fasec_ref_design/fasec_ref_design.xdc
0 → 100644
View file @
7c8b5fb0
set_property PACKAGE_PIN K11 [get_ports areset_n_i]
set_property IOSTANDARD LVCMOS18 [get_ports areset_n_i]
set_property PACKAGE_PIN C8 [get_ports clk_20m_vcxo_i]
set_property IOSTANDARD LVCMOS18 [get_ports clk_20m_vcxo_i]
set_property PACKAGE_PIN U5 [get_ports clk_125m_gtp_n_i]
set_property PACKAGE_PIN U6 [get_ports clk_125m_gtp_p_i]
#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_pllref_p_i]
set_property PACKAGE_PIN G7 [get_ports clk_125m_pllref_p_i]
set_property PACKAGE_PIN F7 [get_ports clk_125m_pllref_n_i]
#set_property IOSTANDARD LVDS_25 [get_ports clk_125m_pllref_n_i]
set_property PACKAGE_PIN N6 [get_ports plldac_sclk_o]
set_property IOSTANDARD LVCMOS18 [get_ports plldac_sclk_o]
set_property PACKAGE_PIN K8 [get_ports plldac_din_o]
set_property IOSTANDARD LVCMOS18 [get_ports plldac_din_o]
set_property PACKAGE_PIN K7 [get_ports pll25dac_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll25dac_cs_n_o]
set_property PACKAGE_PIN N7 [get_ports pll20dac_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll20dac_cs_n_o]
set_property PACKAGE_PIN J14 [get_ports eeprom_sda_b]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_sda_b]
set_property SLEW FAST [get_ports eeprom_sda_b]
set_property PACKAGE_PIN H14 [get_ports eeprom_scl_b]
set_property IOSTANDARD LVCMOS18 [get_ports eeprom_scl_b]
set_property SLEW FAST [get_ports eeprom_scl_b]
set_property PACKAGE_PIN K10 [get_ports thermo_id]
set_property IOSTANDARD LVCMOS18 [get_ports thermo_id]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_sda]
set_property PACKAGE_PIN AB17 [get_ports SFP_sda]
set_property PACKAGE_PIN G16 [get_ports SFP_rx_los]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_rx_los]
set_property PACKAGE_PIN V4 [get_ports SFP_rxp]
set_property PACKAGE_PIN K15 [get_ports SFP_tx_fault]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_fault]
set_property PACKAGE_PIN AB16 [get_ports SFP_scl]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_scl]
set_property PACKAGE_PIN J15 [get_ports SFP_mod_abs]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_mod_abs]
set_property PACKAGE_PIN G14 [get_ports sfp_rate_select_o]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_rate_select_o]
set_property PACKAGE_PIN G15 [get_ports SFP_tx_disable]
set_property IOSTANDARD LVCMOS18 [get_ports SFP_tx_disable]
set_property IOSTANDARD LVDS [get_ports clk_125m_pllref_p_i]
set_property PACKAGE_PIN AC18 [get_ports {pps_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {pps_p[0]}]
set_property PACKAGE_PIN AB26 [get_ports {clk_sys_62m5_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_sys_62m5_p[0]}]
set_property PACKAGE_PIN AE10 [get_ports {clk_ref_125m_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {clk_ref_125m_p[0]}]
set_property PACKAGE_PIN AB22 [get_ports {dio_term[0]}]
set_property PACKAGE_PIN AB10 [get_ports {dio_term[1]}]
set_property PACKAGE_PIN Y13 [get_ports {dio_term[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_term[2]}]
set_property PACKAGE_PIN AB21 [get_ports {dio_oe_n[0]}]
set_property PACKAGE_PIN AD26 [get_ports {dio_oe_n[1]}]
set_property PACKAGE_PIN AF17 [get_ports {dio_oe_n[2]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[1]}]
set_property IOSTANDARD LVCMOS25 [get_ports {dio_oe_n[2]}]
set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_sys]
top/fasec_ref_design/system_top.tcl
0 → 100644
View file @
7c8b5fb0
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