- 26 Jan, 2017 2 commits
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Grzegorz Daniluk authored
Compiled from wrpc-sw: 1c028e8e Merge branch 'minic_fifo' into proposed_master
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Grzegorz Daniluk authored
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- 25 Jan, 2017 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 24 Jan, 2017 5 commits
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Grzegorz Daniluk authored
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Adam Wujek authored
Signed-off-by: Adam Wujek <adam.wujek@cern.ch>
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 20 Jan, 2017 3 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 22 Nov, 2016 16 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 21 Nov, 2016 2 commits
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Maciej Lipinski authored
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Grzegorz Daniluk authored
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- 17 Nov, 2016 8 commits
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
This constraint is needed only when DMTD samples 125m refclock (clock has to be fed to D input of a flip-flop). However, in case of SPEC we use g_divide_input_by_2 generic in the dmtd_with_deglitcher. This re-generates 62.5MHz clock from 125Mhz and we don't feed 125M clock directly to D input of a flip-flop. This constraint would be needed e.g. for Kintex, where refclock is 62.5MHz and we don't use g_divide_input_by_2.
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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Grzegorz Daniluk authored
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- 16 Nov, 2016 1 commit
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Grzegorz Daniluk authored
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