Commit fca0e1bd authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

xwrc_platform_xilinx: missing clk_10m_ref signal assignment

parent 8485bcd9
......@@ -306,6 +306,7 @@ begin
pulse_i => ext_ref_rst_i,
extended_o => ext_pll_rst);
end generate;
ext_ref_o.clk_10m_ref <= clk_10m_ref;
ext_ref_o.pps <= pps_ext_i;
-------------------------------------------------------------------------------
......
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