- 14 Sep, 2017 2 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 13 Sep, 2017 3 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 12 Sep, 2017 10 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
Get first data read.
-
Tristan Gingold authored
-
- 11 Sep, 2017 2 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 08 Sep, 2017 8 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 06 Sep, 2017 4 commits
-
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
- 26 Aug, 2017 1 commit
-
-
Tom Levens authored
-
- 17 Jan, 2017 1 commit
-
-
Tom Levens authored
Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
- 14 Jan, 2017 1 commit
-
-
Tom Levens authored
Move user CR/CSR space to VME64xCore_Top with generic to enable/disable it. Standardise generic default values between VME64xCore_Top and xvme64x_core. Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
- 13 Jan, 2017 3 commits
-
-
Tom Levens authored
Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
Tom Levens authored
Implements DFS feature and FAF in CR/CSR. Note that the DFS is still interpreted incorrectly by the function decoders. Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
Tom Levens authored
Create a port (rst_n_o) on the top level component which is the combination of the HW resets (rst_n_i and VME_RST_n_i) and the SW reset bit coming from the CR/CSR. Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
- 12 Jan, 2017 5 commits
-
-
Tom Levens authored
Remove duplicate registers for all main FSM signals. Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
Tom Levens authored
Assign explicit values to s_XAM, s_phase1addr & s_phase2addr. Remove unused signal s_func_sel. Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
Tom Levens authored
The CR/CSR space has been cleaned up and reworked. All decoding of the addresses has been moved from VME_bus to VME_CR_CSR_Space to make the code a bit more structured.. The option to have a user CR and CSR areas has been added. These are external such that they can be implemented by the user. The custom CSR registers (IRQ vector/level ...) have been moved to VME_User_CSR.vhd. By default (in the xvme64x_core wrapper) this area is mapped to 0x7FF33..7FF5F (in the reserved area) in order to maintain compatibility with the previous version of the core. However, it can be moved using generics to a non-reserved area for new applications. This fixes Bug #1353. Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
Tom Levens authored
The VME_Init component was not needed as all of the CR data comes from generics. Therefore it has been removed to help reduce the footprint of the core (Feature #768). Signed-off-by: Tom Levens <tom.levens@cern.ch>
-
Tom Levens authored
Small bugfix. The IRQ timeout was hardcoded and didn't take into account different clock periods which could be set with the g_clock generic. Signed-off-by: Tom Levens <tom.levens@cern.ch>
-