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VME64x core
Commits
0e9e3c68
Commit
0e9e3c68
authored
Sep 12, 2017
by
Tristan Gingold
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Plain Diff
Simplify vme_bus, rework main FSM.
Get first data read.
parent
0c0cd06f
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4 changed files
with
292 additions
and
441 deletions
+292
-441
VME_Wb_master.vhd
hdl/vme64x-core/rtl/VME_Wb_master.vhd
+6
-6
VME_bus.vhd
hdl/vme64x-core/rtl/VME_bus.vhd
+256
-359
vme64x_pack.vhd
hdl/vme64x-core/rtl/vme64x_pack.vhd
+3
-52
top_tb.vhd
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
+27
-24
No files found.
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @
0e9e3c68
...
...
@@ -27,20 +27,20 @@
--
-- eg of timing diagram with synchronous WB Slave:
--
-- Clk _____ _____ _____ _____ _____ _____
_____
-- _____| |_____| |_____| |_____| |_____| |_____| |
_____|
-- Clk _____ _____ _____ _____ _____ _____
-- _____| |_____| |_____| |_____| |_____| |_____| |
--
-- cyc_o ____________________________________________________________
-- _____| |_____
___________
-- _____| |_____
--
-- stb_o ________________________________________________
-- _____| |_________________
___________
-- _____| |_________________
--
-- __________________________________________
-- stall_i |_____________________________
___________
-- stall_i |_____________________________
--
-- ack_i ___________
-- ______________________________________________________| |_____
___________
-- ______________________________________________________| |_____
--
-- The ack_i can be asserted with some Tclk of delay, not immediately.
-- This component implements the correct shift of the data in input/output
...
...
hdl/vme64x-core/rtl/VME_bus.vhd
View file @
0e9e3c68
This diff is collapsed.
Click to expand it.
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @
0e9e3c68
...
...
@@ -137,7 +137,6 @@ package vme64x_pack is
A64
,
A64_BLT
,
A64_MBLT
,
TWOedge
,
AM_Error
);
...
...
@@ -145,7 +144,6 @@ package vme64x_pack is
SINGLE
,
BLT
,
MBLT
,
TWOe
,
error
);
...
...
@@ -164,52 +162,6 @@ package vme64x_pack is
TWOe_SST
);
type
t_mainFSMstates
is
(
IDLE
,
DECODE_ACCESS
,
WAIT_FOR_DS
,
LATCH_DS1
,
LATCH_DS2
,
LATCH_DS3
,
LATCH_DS4
,
CHECK_TRANSFER_TYPE
,
MEMORY_REQ
,
DATA_TO_BUS
,
DTACK_LOW
,
DECIDE_NEXT_CYCLE
,
INCREMENT_ADDR
,
SET_DATA_PHASE
--UGLY_WAIT_TO_MAKE_DECODING_WORK
-- uncomment for using 2e modes:
--WAIT_FOR_DS_2e,
--ADDR_PHASE_1,
--ADDR_PHASE_2,
--ADDR_PHASE_3,
--DECODE_ACCESS_2e,
--DTACK_PHASE_1,
--DTACK_PHASE_2,
--DTACK_PHASE_3,
--TWOeVME_WRITE,
--TWOeVME_READ,
--TWOeVME_MREQ_RD,
--WAIT_WR_1,
--WAIT_WR_2,
--WAIT_WB_ACK_WR,
--WAIT_WB_ACK_RD,
--TWOeVME_TOGGLE_WR,
--TWOeVME_TOGGLE_RD,
--TWOe_FIFO_WRITE,
--TWOe_TOGGLE_DTACK,
--TWOeVME_INCR_ADDR,
--TWOe_WAIT_FOR_DS1,
--TWOe_FIFO_WAIT_READ,
--TWOe_FIFO_READ,
--TWOe_CHECK_BEAT,
--TWOe_RELEASE_DTACK,
--TWOe_END_1,
--TWOe_END_2
);
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
...
...
@@ -315,7 +267,7 @@ package vme64x_pack is
user_csr_we_o
:
out
std_logic
;
user_cr_addr_o
:
out
std_logic_vector
(
18
downto
2
);
user_cr_data_i
:
in
std_logic_vector
(
7
downto
0
)
:
=
(
others
=>
'0'
);
function_o
:
out
std_logic_vector
(
3
downto
0
);
function_o
:
out
std_logic_vector
(
2
downto
0
);
f0_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f1_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
f2_faf_ader_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
...
...
@@ -353,7 +305,6 @@ package vme64x_pack is
VME_RETRY_OE_o
:
out
std_logic
;
VME_WRITE_n_i
:
in
std_logic
;
VME_DS_n_i
:
in
std_logic_vector
(
1
downto
0
);
VME_DS_ant_n_i
:
in
std_logic_vector
(
1
downto
0
);
VME_DTACK_n_o
:
out
std_logic
;
VME_DTACK_OE_o
:
out
std_logic
;
VME_BERR_n_o
:
out
std_logic
;
...
...
@@ -396,7 +347,7 @@ package vme64x_pack is
component
VME_Funct_Match
is
generic
(
g_ADEM
:
t_adem_array
(
-1
to
7
);
g_ADEM
:
t_adem_array
(
0
to
7
);
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_XAMCAP
:
t_xamcap_array
(
0
to
7
)
);
...
...
@@ -430,7 +381,7 @@ package vme64x_pack is
g_END_USER_CSR
:
std_logic_vector
(
23
downto
0
);
g_BEG_SN
:
std_logic_vector
(
23
downto
0
);
g_END_SN
:
std_logic_vector
(
23
downto
0
);
g_ADEM
:
t_adem_array
(
-1
to
7
);
g_ADEM
:
t_adem_array
(
0
to
7
);
g_AMCAP
:
t_amcap_array
(
0
to
7
);
g_XAMCAP
:
t_xamcap_array
(
0
to
7
);
g_DAWPR
:
t_dawpr_array
(
0
to
7
)
...
...
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
View file @
0e9e3c68
...
...
@@ -33,7 +33,8 @@ architecture behaviour of top_tb is
when
x"d"
=>
return
'd'
;
when
x"e"
=>
return
'e'
;
when
x"f"
=>
return
'f'
;
when
"ZZZZ"
=>
return
'z'
;
when
"ZZZZ"
=>
return
'Z'
;
when
"XXXX"
=>
return
'X'
;
when
others
=>
return
'?'
;
end
case
;
end
hex1
;
...
...
@@ -241,7 +242,7 @@ begin
xor
slave_ga
(
1
)
xor
slave_ga
(
0
));
end
block
;
dut
:
entity
work
.
VME64xCore_Top
vme64xcore
:
VME64xCore_Top
generic
map
(
g_CLOCK_PERIOD
=>
g_CLOCK_PERIOD
,
g_WB_DATA_WIDTH
=>
g_WB_DATA_WIDTH
,
g_WB_ADDR_WIDTH
=>
g_WB_ADDR_WIDTH
)
...
...
@@ -322,6 +323,7 @@ begin
wait
for
(
g_CLOCK_PERIOD
/
2
)
*
1
ns
;
end
process
;
-- Bus timer. See VME spec 2.3.3 Bus Timer
bus_timer_proc
:
process
(
clk_i
)
type
state_t
is
(
IDLE
,
WAIT_DS
,
COUNTING
,
WAIT_END
,
ERR
);
variable
state
:
state_t
;
...
...
@@ -369,18 +371,21 @@ begin
end
if
;
end
process
;
-- WB slave: a simple sram
wb_p
:
process
(
clk_i
)
type
slv_array
is
array
(
0
to
2
**
14
-
1
)
of
std_logic_vector
(
31
downto
0
);
variable
mem
:
slv_array
:
=
(
0
=>
x"0000_0000"
,
1
=>
x"0000_0001"
,
2
=>
x"0000_0002"
,
3
=>
x"0000_0003"
,
4
=>
x"0000_0004"
,
5
=>
x"0000_0500"
,
6
=>
x"0006_0000"
,
7
=>
x"0700_0000"
,
others
=>
x"8765_4321"
);
constant
sram_addr_wd
:
natural
:
=
14
;
type
sram_array
is
array
(
0
to
2
**
sram_addr_wd
-
1
)
of
std_logic_vector
(
31
downto
0
);
variable
sram
:
sram_array
:
=
(
0
=>
x"0000_0000"
,
1
=>
x"0000_0001"
,
2
=>
x"0000_0002"
,
3
=>
x"0000_0003"
,
4
=>
x"0000_0004"
,
5
=>
x"0000_0500"
,
6
=>
x"0006_0000"
,
7
=>
x"0700_0000"
,
others
=>
x"8765_4321"
);
begin
if
rising_edge
(
clk_i
)
then
if
rst_n_o
=
'0'
then
...
...
@@ -392,7 +397,8 @@ begin
ACK_i
<=
'0'
;
if
STB_o
=
'1'
then
if
WE_o
=
'0'
then
DAT_i
<=
mem
(
to_integer
(
unsigned
(
ADR_o
(
13
downto
0
))));
DAT_i
<=
sram
(
to_integer
(
unsigned
(
ADR_o
(
sram_addr_wd
-
1
downto
0
))));
ACK_i
<=
'1'
;
end
if
;
end
if
;
...
...
@@ -512,13 +518,7 @@ begin
wait
for
35
ns
;
VME_AS_n_i
<=
'0'
;
VME_WRITE_n_i
<=
'0'
;
VME_DS_n_i
<=
"10"
;
wait
until
VME_DTACK_OE_o
=
'1'
and
VME_DTACK_n_o
=
'0'
;
VME_DS_n_i
<=
"11"
;
wait
until
VME_DTACK_OE_o
=
'0'
or
VME_DTACK_n_o
=
'1'
;
assert
VME_DATA_DIR_o
=
'0'
report
"bad data_dir_o (wr)"
;
VME_DATA_i
(
7
downto
0
)
<=
data
;
VME_DS_n_i
<=
"10"
;
...
...
@@ -716,17 +716,20 @@ begin
-- Enable card
write8_conf
(
x"7_fffb"
,
b"0001_0000"
);
read8_conf
(
x"7_fffb"
,
d
);
assert
d
=
b"0001_0000"
report
"module must be enabled"
severity
error
;
assert
d
=
b"0001_0000"
report
"module must be enabled"
severity
error
;
report
"read data: "
&
hex
(
d
);
-- WB read
read8
(
x"56_00_00_00"
,
c_AM_A32
,
d
);
report
"read data: "
&
hex
(
d
)
;
assert
d
=
x"00"
report
"bad read at 000"
severity
error
;
read8
(
x"56_00_00_01"
,
c_AM_A32
,
d
);
read8
(
x"56_00_00_07"
,
c_AM_A32
,
d
);
assert
d
=
x"01"
report
"bad read at 007"
severity
error
;
report
"read data: "
&
hex
(
d
);
end
case
;
wait
for
10
ns
;
assert
false
report
"end of simulation"
severity
failure
;
wait
;
end
process
;
...
...
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